Abstract: A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling a secure mode within the programmable IC according to a configuration state of the programmable IC. Enabling secure mode within the programmable IC can provide access to the scan chain. Responsive to enabling the secure mode, the programmable IC can remain in the secure mode and be prevented from re-entering the operational mode until the programmable IC is power cycled.

Abstract: A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters and is detected using differential receiver. One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.

Abstract: A technique applicable during the transfer of data to and from a memory involves: operating a memory interface using memory access cycles that each transfer a quantity of data D across the memory interface; receiving a request to transfer a quantity of data Q across the memory interface; and calculating a value M as a function of a plurality of parameters, M being a minimum number of the memory access cycles needed to carry out the transfer of the quantity of data Q across the memory interface, wherein the calculating includes determining a logarithm of one of the parameters, and then determining the value M as a function of the logarithm.

Abstract: A communication system includes digital signals that carry data and correspond to channels of a composite signal to be transmitted across a communication channel. Active channels are detected and used to configure digital processing. In one embodiment, active channels are detected, where a particular active channel corresponds to the presence of a particular one of the digital signals. Active channel detection may be used to configure pre-distortion of a composite signal to be transmitted to compensate for distortion in a digital-to-analog converter. Likewise, active channel detection may be used to optimize the configuration of an up-converter. In one embodiment, a programmable device is configured based on detected active channels into a plurality of different configurations.

Abstract: In one embodiment, a multi-stage decoder circuit is provided. Each stage of the decoder circuit is configured to perform one or more decoding iterations and produce an error mask indicating errors detected in the decoding stage. A compression circuit is coupled to one or more of the decoder stages and is configured to generate, for each of one or more of the plurality of decoder stages, a respective compressed error mask from the error mask produced by the decoder stage. A buffer circuit is coupled to the compression circuit and is configured to buffer the compressed error masks. A decompression circuit is coupled to the buffer circuit and is configured to decompress each of the compressed error masks. A combination circuit is coupled to the decompression circuit and is configured to combine the decompressed error masks into a single error mask.

Abstract: An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include an isolation wall formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger.

Abstract: A method of using an integrated circuit (IC) can include reading a device code from a selected IC, calculating a measure of randomness from a plurality of values specified within the device code, and comparing the measure of randomness to a randomness criterion. A determination can be made as to whether the selected IC is compromised according to the comparison. An intellectual property (IP) protection method can include determining a list of controlled IP cores within a bitstream specifying a circuit design, creating a bitstream identifier within the bitstream that is associated with the list of controlled IP cores, and determining a count specifying a number of integrated circuits loaded with the bitstream.

Abstract: A packet processing circuit includes a plurality of header extraction circuits, and a scheduling circuit coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus having a plurality of data lanes. In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request, and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes.

Abstract: An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.

Abstract: One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.

Abstract: One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

Abstract: A method of enabling partial reconfiguration in a device having configurable resources is disclosed. The method comprises receiving a configuration bitstream comprising configuration bits; configuring the configurable resources of the device using the configuration bits of the configuration bitstream; receiving a request for a partial reconfiguration of the device; loading updated configuration bits into memory elements associated with a portion of the configurable resources in response to the request for a partial reconfiguration; and providing a status of the partial reconfiguration while loading the updated configuration bits. A circuit for enabling partial reconfiguration in a device having configurable resources is also disclosed.

Abstract: Methods of prioritizing untested routing resources in programmable logic devices (PLDs) to generate test suites that include a minimal number of test designs. The untested routing resources are prioritized (e.g., placed into an ordered list) based on a number of untested input or output terminals for each untested resource. The number of untested input or output terminals (whichever is larger) for each routing resource determines the minimum number of additional test designs in which the routing resource must be included. The resulting prioritization can be utilized by a router, for example, to first include in test designs those routing resources that must be included in the largest remaining number of test designs. The described prioritization methods can also be used to select one of two or more test designs that should be included in the overall test suite. In each case, the overall number of test designs is reduced.

Abstract: A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface.

Abstract: A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first through fourth multiplexers. Each row of a second plurality of routing rows provides a routing path from at least two of the external inputs to at least two of the external outputs. Each routing row of the second plurality of routing rows contains at least one less multiplexer relative to a routing row of the first plurality of routing rows, the one less multiplexer corresponding to at least two external inputs or two external outputs that are logically equivalent to one another.

Abstract: An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.

Abstract: Multiple input multiple output (MIMO) receiver circuitry is described. In one circuit, input circuitry provides a matrix of unresolved symbols received from a plurality of receive antennas. Channel estimation circuitry constructs a plurality of channel matrices including at least two channel matrices corresponding first and second subcarriers, respectively. A preprocessing circuit receives input from the plurality of channel matrices and interleaves retrieved input into an input matrix. A first systolic array includes boundary cells and internal cells. The boundary cells and internal cells are configured to perform triangulation and back-substitution on the input matrix to produce an output matrix. A second systolic array performs right and left multiplication operations and cross-diagonal transpose on the output matrix to produce a weighted matrix.

Abstract: Various methods for inhibiting reverse engineering of a circuit design are provided. In one embodiment, a circuit design is initially mapped to a plurality of identified hardware components of a target device using a first table that indicates a first set of logic patterns that hardware components of the target device can implement. Unused hardware components are identified, and at least one logic pattern of the circuit design is remapped to one of the unused hardware components using a second mapping table. The second table indicates a second set of logic patterns, not indicated by the first mapping table, that one of the unused hardware components is configurable to implement.

Abstract: Approaches for preparing a design of a digital multirate filter. In one approach, an objective function and an input and output characteristic are input for determining an effectiveness of a plurality of filters. The characteristic includes an overall rate change value that specifies a ratio of an input to an output sample rate. The overall rate change value is factored into a plurality of ordered sets, and the overall rate change value is a product of the factors in the ordered sets. Each of the filters corresponds to one of the ordered sets and includes a respective stage for each factor in the ordered set. One of the filters is selected based on respective values determined from evaluating an objective function for the filters, and the factor(s) in the ordered set that corresponds to the selected one of the filters is stored.

Abstract: A method, machine-readable medium, and systolic array for left matrix multiplication of a first matrix and a second matrix are described. The first matrix is a triangular matrix, and a cross-diagonal transpose of the first matrix is loaded into a triangular array of cells in an integrated circuit. A cross-diagonal transpose of the second matrix is input into the triangular array of cells for multiplication with the cross-diagonal transpose of the first matrix to produce an interim result. The interim result is cross-diagonally transposed to provide a left matrix multiplication result, which is stored or otherwise output.