Abstract: According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.

Abstract: A graphical user interface (GUI) used to program complex hardware elements is provided that allows a variety of files to be used to control subsequent content displayed by the GUI. The control includes dynamic updating of actual GUI elements, as well as rule checking based upon data entered into the GUI. Configuration, rule, and GUI files can be used to control the eventual programming of the complex hardware elements. Graphical metaphors are established to enable the viewing of performance information and using that information to control the programming of the complex hardware elements.

Abstract: Systems and methods are provided for identifying an atomic element in proximity to an integrated circuit. Trace amounts of a contaminant are identifiable. The atomic element is exposed to neutron radiation to convert a portion of the atomic element into a radioactive isotope of the atomic element. Upsets are measured for the binary states of the memory cells of the integrated circuit during a time period following the exposure to the neutron radiation. The atomic element is identified from the upsets of the binary states of the memory cells of the integrated circuit.

Abstract: A method of partitioning a circuit design can include identifying a circuit design in which components of the circuit design are assigned to each of a plurality of regions, wherein each region corresponds to a physical portion of an integrated circuit. A maximum oversubscription region can be determined for a selected component type from the plurality of regions. A target region from the plurality of regions can be selected that is adjacent to the region of maximum oversubscription. The method also can include re-assigning, by a processor, a selected number of components of the maximum oversubscription region to the target region.

Abstract: In one aspect, a method for providing encrypted information includes encrypting a true message to form an encrypted true message. A ciphertext message including the encrypted true message is formed, where multiple messages are decryptable from the ciphertext message. The messages include a true message including true information and at least one decoy message including false information.

Abstract: Various approaches for co-simulating an electronic system design are described. In one approach, a hardware design function block in the design is instantiated, along with a specification of a software execution platform including external ports and software to execute on the platform. In response to a user instruction to import the software execution platform into the design, a software execution platform interface block is automatically instantiated. A first simulation model is generated from the hardware design function block and the software execution platform interface block and a second simulation model is generated from the software execution platform. The design is co-simulated using the first and second simulation models. Data is communicated between the first simulation model and the second simulation model via the interface block.

Abstract: A phase detection and decision feedback equalization circuit is provided. A first latch and a second latch are coupled to an input of the circuit. A third latch and a fourth latch are respectively coupled in series to outputs of the first latch and second latch. The first and fourth latches are enabled by a clock signal, and the second and third latches are enabled by a complement of the clock signal. A first feedback circuit is configured to provide a signal output from the first latch and a first feedback signal derived from the output of the fourth latch to an input of the third latch. A second feedback circuit is configured to provide a signal output from the second latch and a second feedback signal derived from the output of the third latch to an input of the fourth latch.

Abstract: Generation of documentation from a computer readable symbolic representation is described. In an embodiment, a reified version of an input is obtained as coded objects. The input is readable by a programmed computer for execution, and is in an applied form of a symbolic representation of knowledge for a defined domain of knowledge. The reified version is a coded form of the applied form, wherein the coded objects are in a dynamic language. A content sequence library is accessed by the programmed computer responsive to the coded objects to extract content for a document plan. A reasoning library is then accessed by the programmed computer responsive to the content extracted to provide a sequenced organization of phrase structure for the content extracted. A natural language representation of the input is output from a realization of the sequenced organization of phrase structure.

Abstract: A channelization circuit channelizes baseband signals in the channels of a wideband signal. The channelization circuit includes a phase shifter, a Fourier transform circuit, filtering circuits, commutator circuits, and a summation circuit. The phase shifter circuit is configured to receive the baseband signals. The Fourier transform circuit is coupled to the phase shifter circuit and configured to frequency translate the baseband signals to the channels of the wideband signal. The filtering circuits are coupled to the Fourier transform circuit, and the commutator circuits are coupled to the filtering circuits. The summation circuit is coupled to the commutator circuits and configured to generate the wideband signal.

Abstract: A decoder, such as for example an MMSE MIMO decoder, and a method for decoding are described. An input channel matrix is obtained, and an extended channel matrix of the input channel matrix is generated. The extended channel matrix is triangularized to provide a triangularized matrix, and the triangularized matrix is inverted to provide an inverted triangular matrix. A left matrix multiplication result matrix associated with multiplication of the input channel matrix and the inverted triangular matrix is generated, and a weight matrix from the left matrix multiplication result matrix and the inverted triangular matrix is generated. A received symbols matrix is obtained, and a weighted estimation is generated and output using the weight matrix and the received symbols matrix to provide an estimate of a transmit symbols matrix for output of estimated data symbols.

Abstract: Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.

Abstract: Nulling a cell of a complex matrix is described. A complex matrix and a modified Givens rotation matrix are obtained for multiplication by a processing unit, such as a systolic array or a CPU, for example, for the nulling of the cell to provide a modified form of the complex matrix. The modified Givens rotation matrix includes complex numbers c*, c, ?s, and s*, wherein the complex number s* is the complex conjugate of the complex number s, and wherein the complex number c* is the complex conjugate of the complex number c. The complex numbers c and s are associated with complex numbers of the complex matrix including the cell to be nulled. The modified form is then output by the processing unit. The modified Givens rotation matrix may be implemented as a systolic array or otherwise used for processing complex numbers or matrices.

Abstract: Approaches for preparing a system that is reconfigurable to implement a plurality of optional hardware functions are disclosed. In one approach, a method includes simulating the operation of the system during a time interval. The system is reconfigurable to implement a subset of the optional hardware functions, and the simulating determines which of the optional hardware functions are active and which of the optional hardware functions are inactive during a plurality of subintervals of the time interval. Respective circuit resource sets are estimated for the subintervals of the time interval. For each of the subintervals, the respective circuit resource set implements the system including the optional hardware functions that are active during the subinterval. Information describing the respective circuit resource sets for the subintervals is stored for preparing partial reconfigurations of the system.

Abstract: Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.

Abstract: A communication system includes an iterative multi-stage decoder that may be dynamically configured to achieve a particular bit-error-rate. In one embodiment, a circuit comprises a first decoder block and a second decoder block to decode data received over a communication channel. A control circuit may change a number of iterations performed by the decoder blocks to decode received data based on a specified bit error rate and a detected signal-to-noise ratio of said received data. The number of computational units used in the decoders may be changed dynamically to achieve desired system performance. In one embodiment, resources are allocated based on a system initiating the connection. Programmable circuits are used in some embodiments to reconfigure the multi-stage decoder.

Abstract: Approaches for generating a hardware specification from a high-level language (HLL) program. In one approach, a method determines separate accesses in the HLL program to multiple consecutively addressed data items. The HLL program is compiled into an intermediate language program to include one or more instructions that perform functions on the multiple consecutively addressed data items and one or more memory access instructions that reference the consecutively addressed data items. The method generates a hardware specification from the intermediate language program. The hardware specification includes a cache memory that caches the consecutively addressed data items and that accesses the consecutively addressed data items in response to a single access request. The specification further includes one or more hardware blocks that implement the functions of the instructions in the intermediate language program.

Abstract: A memory arrangement includes a plurality of memory blocks, a first group of access ports, and a second group of access ports. Routing circuitry couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block, and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion, and has read access to the first portion but not to the second portion.

Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.

Abstract: A floating-point adder circuit is described. The circuit comprises an input multiplexer coupled to receive a first input value and a second input value; an adder-subtractor circuit selectively coupled to receive one of the first input value and the second input value at each of a first input and a second input, wherein the value coupled to the second input is added to or subtracted from the value coupled to the first input; a right shift circuit for aligning the smaller of the first input value and the second input value which is coupled to the second input of the adder-subtractor circuit; and an additional shift circuit (e.g., a left shift/right shift circuit of a combined near path and far path) coupled to the output of the adder-subtractor circuit. A method of implementing a floating-point adder is also disclosed.

Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.