Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.

Abstract: An integrated circuit has a transistor with an active gate structure overlying an active diffusion area formed in a semiconductor substrate. A dummy gate structure is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer overlying the transistor array produces stress in a channel region of the transistor.

Abstract: Method, apparatus, and computer readable medium for performing electrical rule checks (ERCs) on a circuit design are described. In one example, a hierarchy of cell instances is created from a schematic database for the circuit design. The hierarchy is traversed to produce master nets. Each of the master nets is associated with shorted nets in the circuit design. The hierarchy is traversed to produce ERC nets. Each of the ERC nets is associated with effectively shorted nets in the circuit design. At least one pair of the effectively shorted nets is effectively shorted across a transistor. At least one ERC is performed on the circuit design using the master nets and the ERC nets.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: A programmable integrated circuit performs an initial partial configuration of the programmable integrated circuit in response to receiving an activation signal. In this way, the programmable integrated circuit enables an initial functionality of the programmable integrated circuit. The programmable integrated circuit then performs a subsequent partial configuration of the programmable integrated circuit for enabling additional functionality of the programmable integrated circuit. In some embodiments, the programmable integrated circuit receives an input signal indicating a stimulus in an environment of the programmable integrated circuit and determines based on the input signal whether to perform the subsequent partial configuration of the programmable integrated circuit or generate a power down signal for powering down the programmable integrated circuit without performing the subsequent partial configuration.

Abstract: A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer interface, programmable resources coupled to the embedded controller via a client interface, tie-off pin inputs coupled to the embedded controller for receiving a configuration vector for configuring the embedded controller without having to use a microprocessor for such configuration with the client interface being for communication between the embedded controller and the programmable resources for access to and from the network, and the embedded controller including a multi-mode interface coupled to the client interface for coupling to the programmable resources, the multi-mode interface including a plurality of Media Independent Interface modes, the multi-mode interface configured to be coupled to the physical layer interface.

Abstract: Method and apparatus for processing scalable content having a base layer and at least one enhancement layer is described. In one example, static logic having decoder logic and system monitor logic is provided. Programmable logic having a plurality of reconfigurable slots is also provided. The decoder logic includes a base layer processor for processing the base layer of the scalable content. The system monitor logic is configured to dynamically reconfigure at least one of the plurality of reconfigurable slots with at least one enhancement block for processing the at least one enhancement layer of the scalable content.

Abstract: Methods of placing and routing a logic design are provided. The logic design includes logic elements and nets connecting the logic elements. A first placement and a partial routing of the logic elements and the nets of the logic design are generated. The partial routing leaves some of the nets unsuccessfully routed. An initial area associated with each of the logic elements is expanded for the logic elements that are connected to the unsuccessfully routed nets. Positions for the logic elements are determined from a linear system that reduces a total length of the nets connecting the logic elements and inhibits overlap of the areas of the logic elements. A second placement of the logic elements is generated from the positions. A complete routing of all of the nets is generated for the second placement. A specification of the second placement and the complete routing is output.

Abstract: Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.

Abstract: A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.

Abstract: Disclosed is a recursive, direct digital synthesizer includes an accumulator module and a Coordinate Rotation Digital Computer (CORDIC) module coupled to the accumulator module. The CORDIC module rotates a signal according to a desired rotation angle specified by the accumulator module. An automatic gain control module is coupled to the CORDIC module. The automatic gain control module can apply a level of gain to the rotated signal.

Abstract: An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.

Abstract: A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE) in a unified signaling system. An input data stream is sliced into an even data stream and an odd data stream, whereby the sliced data is compared to a programmable threshold depending upon a detection mode. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, a correct portion of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is summed in current mode with the feedback data and converted to voltage prior to sampling the currently received data bit.

Abstract: An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.

Abstract: A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.

Abstract: Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.

Abstract: A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.

Abstract: A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponents as between corresponding first adjusted values. A first operation specific floating-point processing unit (OFPU) is coupled to receive the first adjusted values and includes first arithmetic circuitry configured for a first floating-point operation on the first adjusted values to provide first numerical results. The first numerical results are not normalized prior to a second floating-point operation.

Abstract: Method and apparatus for designing an embedded system for a programmable logic device (PLD) is described. Parameters specific to the embedded system are obtained. Source code files that use the parameters to define configurable attributes of the base platform are generated. A software definition and a hardware definition are obtained. The software and hardware definitions each use an application programming interface (API) of the base platform to define communication between software and hardware of the embedded system. An implementation of the embedded system is automatically built for the PLD using the source code files, the software definition, and the hardware definition.

Abstract: Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.