Abstract: Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.

Abstract: Systems and methods are provided for verifying respective configuration data values for programming configuration memory cells of an integrated circuit device such as a programmable logic device (PLD). Each configuration memory cell controls an input of a corresponding initialization value from a file in response to a selectable assertion of an initialization signal of a test bench during a logic simulation of the PLD. The file structurally associates the configuration memory cell with the corresponding initialization value. A current value of one or more of the configuration memory cells is written with the respective configuration data value via a configuration port of the PLD during the logic simulation. Each configuration memory cell compares its initialization and current values in response to a selectable assertion of a check signal of the test bench. A mismatch error is output in response to a difference between the initialization and current values of one or more of the configuration memory cells.

Abstract: A direct memory access engine is described. The direct memory access engine has a transmit channel coupled to a transmit interface, a receive channel coupled to a receive interface, an arbiter coupled to both the transmit channel and the receive channel, and a set of queues coupled to the arbiter. The set of queues has command buffers, transmit buffers, and receive buffers. A direct memory access-to-processor bus interface is coupled to the set of queues. The transmit buffers are for first separate read and write requests. The receive buffers are for second separate read and write requests which are independent of the first separate read and write requests.

Abstract: A cycle basis is efficiently determined for a directed graph. A first depth-first search of the directed graph classifies each of the edges of the directed graph to have a type that is one of a within-tree type for an edge within a tree of the first depth first search, a forward type for an edge skipping forward along the tree, a back type for an edge directed back along the tree, or a cross type for an edge between two subtrees of the tree. A second depth-first search of the directed graph determines a respective cycle for each of the edges of the back type. A third depth-first search of the directed graph determines a respective cycle for each of the edges of the cross type that is included a cycle. The basis is output the basis that specifies each of the respective cycles.

Abstract: Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

Abstract: Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.

Abstract: A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.

Abstract: A molded integrated circuit package is described. The molded integrated circuit package comprises a substrate having a plurality of contacts on a first surface; a die having a plurality of solder bumps on a first surface, the plurality of solder bumps being coupled to the plurality of contacts on the first surface of the substrate; an adhesive material positioned on a second surface of the die; a lid attached to the adhesive material; and an encapsulant positioned between the lid and the substrate. Methods of forming molded integrated circuit packages are also disclosed.

Abstract: A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (Rsub) that initiates bipolar snapback in the MOSFET output driver at which an ESD event occurs. The value of Rsub depends upon a composite distance from the centroid of each MOSFET output driver to the contact ring.

Abstract: An implementation of a logic description is improved. The implementation has two signals coupled to two inputs of a fanout-free cone. A swap function is determined of the inputs of the fanout-free cone. The swap function indicates whether there is a difference at an output of the fanout free cone between the fanout-free cone with and without swapping the two signals between the two inputs of the fanout-free cone. A do-not-care function of the inputs of the fanout-free cone is determined for the logic description. The do-not-care function indicates that a modification of the output of the fanout-free cone is not observable at the primary outputs of the logic description. A modified implementation of the logic description is output in response to the do-not-care function covering the swap function. The modified implementation of the logic description has the two signals swapped between the two inputs of the fanout-free cone.

Abstract: A test work station for testing ICs includes an output bench with sliding rails that partitions the table top of the output bench into segregated areas. ICs that pass testing are sorted according to an operating parameter, in other words binned, and placed in the appropriate segregated area. The sliding rails avoid mingling of the various categories (bins) of ICs. In a further embodiment, the test work station includes an input bench for receiving product. Failed ICs are kept on the input bench, thus segregating them from ICs that have passed testing and avoiding inadvertent mixing of bad ICs with good ICs. In a particular embodiment, the input and output benches are at a height that allows an operator to stand while working, and allows storage underneath the benches to keep the work areas clear.

Abstract: A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity PSV generator, such that the need for multiplication operations is obviated. Each evaluation cycle performed by the reduced complexity PSV generator is modified by each primitive root of the desired discrete power series. For each PSV generated, a corresponding address is calculated to indicate the correct placement of the PSV generated.

Abstract: Methods and apparatus for configuring a programmable integrated circuit are described. In one example, a configuration stream having first data for programming first locations in a configuration memory and an instruction for referencing circuitry in the programmable integrated circuit is received. Second data is obtained from the circuitry based on the instruction. Second locations in the configuration memory are programmed in response to the second data.

Abstract: A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.

Abstract: Method and apparatus for translating a first program in a dynamically-typed language to a program in a hardware description language. From the dynamically-typed-language first program, a second program in single static assignment format is generated. For cases where a variable is assigned different data types at different places in the program, the assignments of the different data types are resolved for the variable. The second program is then translated to a program in the hardware description language.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.

Abstract: An Add-Compare-Select circuit for use with a trellis decoder can include a first module and a second module. The first module can provide a difference signal specifying an indication of a difference between a second path cost and a first path cost of a trellis. The second path cost can be a sum of a second state cost and a second branch metric and the first path cost can be a sum of a first state cost and a first branch metric. The second module can select the first path cost or the second path cost as a new cost according to the difference signal of the first module.

Abstract: A method of communicating data among a plurality of software modules of a heterogeneous software system can include constructing an XTable object in a first software module of the plurality of software modules and providing the XTable object to a second software module of the plurality of software modules. The method further can include extracting data from the XTable object within the second software module.

Abstract: An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.