Abstract: A method communicates data with efficient conversion between representations in a high-level modeling system. The data is communicated from a first block in a first external format and the data is communicated to a second block in a second external format. The first block has a first internal representation of the data and the second block has a second internal representation of the data. The first internal representation is converted to the second internal representation without intermediate representation in the first and second external formats in response to different first and second external formats or different first and second internal representations. Conversion between the representations of the data is bypassed in response to like first and second external formats and like first and second internal representations. A signal instance is created that communicates the data between the blocks. Converters between data representations are installed in the signal instance on demand.

Abstract: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

Abstract: An on-chip stuck-at fault detector in an integrated circuit using a test circuit for critical path testing can include a sequence circuit having a first sequential circuit and a second sequential circuit to sensitize the critical path between a source sequential circuit and a destination sequential circuit, an analyzer circuit for capturing an output from the destination sequential circuit and comparing a signal between the destination sequential circuit and the analyzer circuit at predetermined clock cycles, and a controller for strobing the analyzer circuit at the predetermined clock cycles. The first sequence and second circuits can both be initialized to a zero mode (e.g., x=0 and y=0). Thus, no stuck-at faults are determined if the destination sequential circuit and an analyzer sequential circuit in the analyzer circuit have different values and a zero result is captured at a sticky-bit flip flop.

Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

Abstract: A method of estimating jitter for a DFS can include determining a plurality of linear equations, wherein each linear equation corresponds to, at least in part, a combination of multiplier and divisor attributes for setting an output frequency of the DFS, identifying maximum and minimum values for the slope component and the vertical axis intercept component from the plurality of linear equations, providing an equation for determining minimum jitter given, at least in part, an input frequency, and providing an equation for determining maximum jitter given, at least in part, an input frequency. A linear equation can be derived for estimating jitter of the DFS according to a specified input frequency and a specified value of the divisor attribute of the DFS. The linear equation further can depend upon the minimum jitter and the maximum jitter.

Abstract: Disclosed is a method of fabricating an integrated circuit assembly in which a plurality of mother dice having a plurality of through-die vias (TDVs) are formed in the first (active) surface of a semiconductor wafer, a substrate is attached to the active surface of the wafer, the second (inactive) surface is back-ground to expose one end of the through-die vias, a plurality of daughter dice are mounted to the inactive surface of the wafer, each daughter die being electrically coupled to a mother die, and the mother dice are then singulated. Attaching the substrate can be accomplished by adhering a glass wafer carrier to the wafer. The wafer carrier allows handling of the wafer during back-grinding the inactive surface, forming under-bump metal (UBM) pads on the TDVs and attaching the daughter dice.

Abstract: A method and apparatus is provided for the implementation of a measurement and adjustment mechanism within a semiconductor die that facilitates adjustment of the magnitude of voltage generated by one or more voltage reference generation circuits on the die. In a first embodiment, the output voltage magnitude of a bandgap reference circuit may be measured and adjusted. In a second embodiment, the output voltage magnitude of a voltage regulator circuit may be measured and adjusted. Programmable circuit elements, such as programmable resistors, may first be programmed during a configuration event of the die to determine the optimal configuration settings of the one or more voltage reference generation circuits. The optimal configuration settings are then used to program the state of one or more eFuses to maintain the optimal configuration settings for the duration of the semiconductor die's lifetime.

Abstract: A scan element with self scan-mode toggle is described. In an example, the scan element is configured to automatically switch between a capture mode and a scan mode. In the capture mode, data is captured from logic under test. In the scan mode, the captured data is scanned out for testing. The scan elements each include a shift register that serves a dual purpose of providing control for determining when the scan element is to switch from the capture mode and the scan mode, as well as providing a location to store captured data.

Abstract: An arrangement and method of reducing power in bidirectional I/O ports includes driving an input signal from an I/O port by asserting a high impedance (Hi-Z) signal to an output drive, driving an output signal from the I/O port by refraining from asserting a Hi-Z signal to an output driver, and feeding back the output signal to an input driver when driving the output signal. The method can float the I/O port when the Hi-Z signal is asserted on the output driver or drive the I/O port as an input when the Hi-Z signal is asserted on the output driver. The method can refrain from floating a signal back into the I/O port when driving a signal out by driving a constant logical zero back into the I/O port or driving a constant logical one back or by maintaining a last value driven.

Abstract: A method and apparatus involving a circuit is disclosed. The circuit has separate first and second portions, where the first portion includes a first memory device such as a flip-flop, and the second portion includes a second memory device such as a latch. The first portion is selectively operated in first and second operational modes, the first portion consuming less power in the second operational mode than in the first operational mode. During the first operational mode a logical value is maintained in the flip-flop and can vary dynamically. During the second operational mode, the state that the logical value had at a point in time just before the first portion entered the second operational mode is maintained in the latch. Then, after the first portion switches from the second operational mode back to the first operational mode, the state of the logical value in the latch is restored to the flip-flop.

Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.

Abstract: Systems and methods detect a communication received at receiving antennas from transmitting antennas. Each transmitting antenna transmits a symbol in a constellation. A sphere detector performs a depth-first search until the depth-first search terminates in response to a terminate signal requesting the result from the sphere detector. The depth-first search evaluates respective distances of one or mode leaf nodes in response to the communication received at the receiving antennas. The depth-first search selects the result from these nodes in response to the respective distances. The result includes a selected leaf node that identifies a corresponding symbol in the constellation for each transmitting antenna, with this symbol detected as transmitted by the transmitting antenna.

Abstract: An integrated circuit includes an auto-bridging architecture including a first phases block that interfaces to a first user block having a first user signal domain. The first phases block converts the first user signal domain to a common signal domain. A second phases block coupled to the first phases block interfaces with a second user block having a second user signal domain. The second phases block converts the second user signal domain to the common signal domain so that the first user block cooperates with the second user block through the auto-bridging architecture of the IC.

Abstract: Methods of using one of a plurality of configuration bitstreams in an integrated circuit are disclosed. An exemplary method comprises analyzing the plurality of implementations of a design to determine initial variations in timing among the implementations; modifying the implementations to reduce the variations in timing among the implementations; and outputting a plurality of configuration bitstreams for the implementations having variations in timing that are reduced relative to the initial variations in timing. Another method comprises generating a plurality of implementations for the design; generating a cost function for the design based upon costs (e.g.

Abstract: An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.

Abstract: A method of implementing a circuit design for a target device can include assigning load pins of a high fanout signal of a placed circuit design into a plurality of windows according to a location of each load pin on the target device. A source of the high fanout signal can be replicated, wherein each window is associated with a source of the high fanout signal. For each source of the high fanout signal, the source can be connected to load pins of the window associated with the source and the source can be placed within the window associated with the source. The placed circuit design can be output.

Abstract: An integrated circuit (“IC”) with a peripheral component interconnect express (“PCIe”) has at least two data sinks (204, 206) and a data source (202) capable of providing data packets to either data sink. A switch (208) of the PCIe system includes a first buffer (226) queuing data packets for one of the data sinks and a second buffer (227) queuing data packets for the other data sink. A status detector (224) detects when the first buffer equals or exceeds a selected buffer threshold, and a status-based flow control transmitter (232) sends a data link layer packet (“DLLP”) to the status-based flow control receiver (234) of the data source to cease transmitting first data packets while continuing to transmit second data packets.

Abstract: A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallographic directions, but exhibit an etch rate that is much slower in a second crystallographic direction. As such, one dimension of the etching process is time controlled, a second dimension of the etching process is self-aligned using sidewall spacers of the gate stack, and a third dimension of the etching process is inherently controlled by the selective etch phenomenon of the selective etchant along the second crystallographic direction. A deeper trench is implemented by first forming a lightly doped drain (LDD) region under the gate stack and using the sidewall spacers in combination with the LDD regions to deepen the trenches formed within the semiconductor material.

Abstract: A circuit structure for determining a period of time during which a device was without power is disclosed. The circuit structure comprises a volatile memory storing known data and a test circuit coupled to the volatile memory, the test circuit determining an amount of incorrect data stored in the volatile memory after a period of time during which the device was without power. The amount of incorrect data is used to determine the period of time during which the device was without power. A method of controlling a device based on the amount of incorrect data stored in a volatile memory after the device was without power is also disclosed. For example, the device can be controlled by altering a start-up sequence of one or more elements of the device.

Abstract: An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.