Abstract: A method and apparatus involves operating a circuit having a test circuit interrupt input terminal (INTERRUPT), having a test circuit clock output terminal (DUT_CLK), and having first and second operational modes. In the first operational mode the circuit supplies a test circuit clock signal to the test circuit clock output terminal. The circuit responds to receipt of an occurrence of a test circuit interrupt at the test circuit interrupt input terminal by then operating in the second operational mode. In the second operational mode the circuit refrains from supplying the test circuit clock signal to the test circuit clock output terminal.

Abstract: A method of configuring a plurality of memory elements having selectable dimensions, the method comprising the steps of selecting a width of a data word to be output by a circuit having the plurality of memory elements; selecting a width for memory locations of the plurality of memory elements, the width for the memory location being less than the width of a data word; configuring the plurality of memory elements to have the selected width; and concatenating the outputs for the plurality of memory elements to generate a concatenated output comprising a data word. A circuit for configuring a plurality of memory elements having selectable dimensions is also disclosed.

Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

Abstract: In one embodiment of the present invention, a programmable interconnect circuit is provided. The programmable interconnect circuit includes first and second static random access memory cells, each having a first output and a second output. The second output is an inversion of the first output. First and second pass gates are each coupled to one of the first and second outputs of the respective first and second memory cells. First and second lock-state circuits are coupled to the respective first and second memory cells. In response to a configuration status signal and the first output of one of the memory cells being asserted to a low voltage, the respective lock-state circuit is configured to maintain the one of the outputs of the respective memory cell at the low voltage.

Abstract: A programmable encryption approach involves the use of a downloadable decryptor. According to an example embodiment of the present invention, an FPGA device includes a microcontroller for configuring logic circuitry on the FPGA device. A memory register is implemented for storing encryption key data and a message authentication code (MAC). When the FPGA device is to be configured using a configuration bitstream, a MAC is calculated for a decryptor and sent to the microcontroller along with an encryption key. The microcontroller stores the encryption key and MAC in a register to which access is limited. When the decryptor is downloaded to the microprocessor, a MAC is calculated on the downloaded decryptor and compared with the stored MAC. If the calculated MAC matches the stored MAC, the decryptor is allowed to access the key.

Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

Abstract: In one embodiment of the invention, a method is provided for protecting against single event upsets of a circuit in programmable logic. Configuration memory cells of the programmable logic are configured to implement first and second copies of the circuit. In response to detecting a single event upset of one of the configuration memory cells, an address of the one of the configuration memory cells is determined. The one of the first and second copies of the circuit in which the single event upset occurred is determined from the address of the one of the configuration memory cells. The output from the one of the first and second copies of the circuit in which the single event upset did not occur is selected as an output of the circuit.

Abstract: A method and apparatus for efficient drive level selection for, e.g., power amplifiers utilized within a wireless communication system, which utilizes digital predistortion (DPD) to adaptively and predictively select drive level. The DPD, e.g., increases the power amplifier's efficiency while maintaining spectral mask compliance within the designated frequency band of transmission. The method first determines a peak amplitude of an undistorted waveform that is to be transmitted and then predicts the maximum power that is to be transmitted by the power amplifier after the undistorted signal has been predistorted. An over-drive metric is then calculated based upon the predicted drive level of the power amplifier, which indicates whether or not the cascade of the predistorter and the power amplifier is predicted to operate linearly. The over-drive metric may then be used to ensure optimal power amplifier performance, thereby eliminating the need to use overly conservative power amplifier drive settings.

Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.

Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Abstract: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.

Abstract: Various approaches for profiling a target system are described. In one approach, a uni-directional, point-to-point bus has a single input port and a single output port. A target processor has a trace port coupled to the input port of the bus and is configured to execute a plurality of instructions one or more times. The target processor provides state data at the trace port and to the input port of the bus. A profile circuit arrangement is coupled to the output port of the first bus, and a memory is coupled to the profile circuit arrangement. The profile circuit arrangement is configured to read data from the output port of the first bus and write the data to the memory.

Abstract: In a method of optimizing power consumption in an integrated circuit, a physically implemented circuit design meeting at least one timing constraint is provided. A design block of the physically implemented circuit design having a high toggle rate pattern is identified. A power optimized transformation type of numerous power optimized transformation types is selected. The power optimized transformation type is applied to the design block of the physically implemented circuit design. A modified physically implemented circuit design is generated, where the modified physically implemented circuit design is power optimized.

Abstract: A computer-implemented method of performing timing analysis upon a circuit design having synchronous circuit elements can include selecting a destination pin having a plurality of source pins, wherein each source pin of the plurality of source pins defines a data path to the destination pin. A slack of a selected path of the data paths to the destination pin can be determined. A timing adjustment of each of the plurality of source pins can be compared to the slack of the selected path, wherein each timing adjustment is determined using static timing analysis. A simulation node can be selectively included within the circuit design according to the comparison. The circuit design can be output.

Abstract: Approaches for automatically generating a format of a plurality of fields of a plurality of packets of a communication protocol from a specification. The specification that is input specifies the fields of the packets of the communication protocol and indicates a plurality of dependencies between the fields. From the specification, an order of the fields is generated for satisfying the dependencies. The format, which is output, specifies the order for inputting and outputting the fields in each of the packets.

Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

Abstract: An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.

Abstract: A socket for an integrated circuit is disclosed. The socket comprises a main body portion having a plurality of holes extending between a top surface and a bottom surface; an overlay positioned adjacent to the main body portion and having a plurality of holes corresponding to the plurality of holes of the main body portion, wherein the overlay comprises a plurality of conductors between holes; and a plurality of contact elements positioned in predetermined holes of the main body portion. A method of providing a connection in a socket is also disclosed.

Abstract: A method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.

Abstract: The availability of device resources of an IC are quantified for a circuit design by building a representation of resource sites for the IC. Initial availability values are assigned to the resource sites, and any components having locking constraints are identified and placed into their respective sites. From the remaining resource sites, candidate sites for a component of the circuit design are identified. The candidate sites are summed, and the initial availability values of the candidate sites are modified according to the sum.