Abstract: Approaches for sizing first-in-first-out (FIFO) buffers for pipelining functions of a circuit. Functions of the circuit are performed on an input data set, with respective FIFO buffers for buffering data elements between coupled pairs of the functional blocks. While performing the functions of the circuit, a respective current number of elements added to a FIFO buffer since a previous element was removed from the FIFO buffer is counted for each FIFO buffer, and then compared to a respective saved number. The respective current number is saved as a new respective saved number in response to the respective current number being greater than the respective saved number, and the respective current number is reset after the comparing of the respective current number to the respective saved number. Respective sizes for the FIFO buffers are determined as a function of the respective saved numbers and then the sizes are stored.

Abstract: A circuit configuration for a pipeline core to be implemented in a programmable integrated circuit (IC) is dynamically specified by providing a single code set embodying an expanded netlist representative of a dynamic circuit configuration of the pipeline core. The code set, which includes one or more parameter variables that determine the length and width of the implemented pipeline core, is synthesized by setting the parameter variables to selected constant values to generate a reduced netlist embodying a static circuit configuration for the implemented pipeline core.

Abstract: An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.

Abstract: Multiple-Input, Multiple-Output Orthogonal Frequency Division Multiplexing (“MIMO-OFDM”) modulation is described. An integrated circuit has blocks of memory of a fixed size. A physical layer block is configured for MIMO-OFDM. The physical layer block is a single MIMO-OFDM block for supporting transmitting via a plurality of antennas. The physical layer block includes buffers configured for storing sets of symbols at a time for transmitting via the plurality of antennas.

Abstract: A method and apparatus for improving enforcement of the time-limited operation of a programmable device. Two random number generators, e.g., linear feedback shift register (LFSR) circuits, are utilized in which a first LFSR provides free-running capability, while a second LFSR provides time-sensitive capability. The states of the two LFSR circuits are compared by various portions of the programmable device at each state transition in order to obtain authorization to continue operation. Authorized operation continues as long as the states of both LFSRs are equivalent, or at least equivalent, within a given phase offset. Once a terminal count of the time-sensitive LFSR is reached, then authorization for continued operation ends and at least a portion of the programmable device is disabled.

Abstract: A method of profiling a hardware system can include compiling a high level language program into an assembly language representation of the hardware system and translating instructions of the assembly language representation of the hardware system into a plurality of executable, software models. The models can be implemented using a high level modeling language for use with cycle accurate emulation. The method also can include instrumenting at least one of the plurality of models with code that, when executed, provides operating state information relating to the model as output and indicating expected behavior of the circuit by executing the models in an emulation environment.

Abstract: A method of protecting a circuit design implemented within an integrated circuit (IC) from electrostatic discharge (ESD) can include positioning a device array pair comprising first and second device arrays on the IC to share a common centroid, wherein the first and second device arrays are matched. An ESD diode array pair comprising first and second ESD diode arrays can be positioned on the IC adjacent to a first perimeter encompassing the first and second device arrays, wherein the first and second ESD diode arrays share the common centroid and are matched. A cathode terminal of each ESD diode of the first ESD diode array can be coupled to an input of the first device array, and a cathode terminal of each ESD diode of the second ESD diode array can be coupled to an input of the second device array.

Abstract: An integrated circuit includes a pass gate having an input and an output. An NMOS pass transistor is connected between the input and the output. The drain of the NMOS pass transistor is connected to the input and the source of the NMOS pass transistor is connected to a node between the source of the NMOS transistor and the output of the pass gate. A current clamp is connected between the node and a current sink so as to conduct current to the current sink when the node reaches a threshold value.

Abstract: A method of suppressing noise in a circuit is disclosed. The method comprises providing a supply voltage to a first terminal of the circuit; providing a ground voltage to a second terminal of the circuit; providing a clock signal to the circuit; and actively decoupling noise from at least one of the first terminal and the second terminal of the circuit by actively decoupling noise synchronously with the clock signal. A circuit for suppressing noise in a circuit is also disclosed.

Abstract: A computer-implemented method of technology mapping a circuit design for implementation within a programmable logic device can include determining a plurality of cut sets for the circuit design, wherein each cut set includes a plurality of cuts. The method can include evaluating each cut set according to a cost function that depends, at least in part, upon a measure of inter-cut symmetry and selecting a cut set according to the cost function. Each cut of the selected cut set can represent an instantiation of at least one logic component within the programmable logic device. The circuit design specifying the selected cut set can be output.

Abstract: A method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.

Abstract: A method estimates the effective switched capacitance for any number of resource types that may be used to form a yet-to-be fabricated IC device using pre-layout netlists of the various resource types. The effective switched capacitances of the resource types are then combined with the operating frequency and the resource utilization of a user design to estimate the power consumption of the user design to be implemented in the device before physical samples of the device are available.

Abstract: Methods of detecting unwanted logic in a configuration bitstream for a programmable logic device (PLD). The bitstream can be reversed engineered to generate a model of the design. The model is then tested for unwanted logic, e.g., logic inserted for the purpose of monitoring or interfering with the desired functionality of the design, by applying a test suite that exercises all desired functions for the design. If some of the logic nodes in the model are not exercised by the test suite, then the unexercised nodes might constitute unwanted logic and might have been inserted for malicious purposes. To reverse engineer the bitstream, a simulation model of the unprogrammed PLD can be used. Configuration bits from the bitstream can be inserted into the model of the unprogrammed PLD. The modified model can be simplified by propagating constants through the model in response to the values inserted into the model.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: A method of managing correlation data for a design implementation process can include identifying correlation data from each of a plurality of design applications. Each of the design applications can generate a circuit description and the correlation data can specify associations between circuit elements of different ones of the circuit descriptions. The method also can include storing the circuit descriptions and the correlation data independently of one another and determining a relationship among circuit elements of the circuit descriptions according to the correlation data.

Abstract: A Turbo Code decoder for implementation in an integrated circuit is described. An add-compare select (“ACS”) unit is configured to provide a difference between first and second outputs and to select one of the first and second outputs responsive to a difference thereof. An initialization stage is coupled to receive and configured to store for example the first output selected as an initialization value. A second select stage is coupled to receive for example the first output selected from the first select stage and coupled to obtain the initialization value stored from the initialization stage. The second select stage is configured to output either the first output selected from the ACS unit or the initialization value from the initialization stage.

Abstract: Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams for a circuit design is disclosed. The method comprises analyzing a plurality of implementations for the circuit design; determining minimum timing constraints based upon all of the implementations for the circuit design; generating a representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints for all of the implementations of the circuit design; and outputting the representative implementation.

Abstract: A system detects symbols communicated from multiple transmitting antennas to multiple receiving antennas. A first detector determines the symbols from respective partial distances of potential choices for symbols from a constellation. A second detector determines the symbols from respective partial distances of more potential choices. The first and second detectors determine their partial distances from signals received at the receiving antennas. The second detector has a lower bit error rate than the first detector. The potential choices for the second antenna are smaller than the potential choices for the first antenna in response to a signal-to-noise ratio (SNR) being higher than a threshold. An evaluator estimates the SNR of the signals received at the receiving antennas. The evaluator enables the first detector in response to the SNR being lower than the threshold, and the evaluator enables the second detector in response to the SNR being higher than the threshold.

Abstract: A method and apparatus is provided for a configurable input/output (I/O) interface within an integrated circuit to support a plurality of I/O standards. The configurable I/O interface exhibits a default operation that facilitates hot-swappability, which eliminates current paths within the I/O interface that may be created during plug-and-play operation of the I/O interface. The current paths are eliminated within the I/O interface even while the I/O interface is not receiving operational power, or while the I/O interface is in a power-on reset condition. A programmable option of the configurable I/O interface, on the other hand, alleviates over-voltage conditions while the I/O interface is tri-stated by activating shunt circuitry to conduct a clamp current during the over-voltage condition. The over-voltage condition is further alleviated by passively establishing current paths through existing circuitry within the I/O interface for the duration of the over-voltage condition.

Abstract: Apparatus and method for performance monitoring is described. Instances of performance monitors are loaded into configurable resources. The performance monitors are coupled to a processor via an auxiliary processor unit or a debug port to obtain processor pipeline execution status. Real-time threads or processes are loaded into memory for execution by the processor. The performance monitors are used to monitor the execution status of the real-time threads or processes executed by the processor.