Abstract: A programmable logic block provides an improved output delay by bypassing the memory array and multiplexer structure when programmed to function as a random access memory (RAM) and a new value is written to the RAM. A programmable logic block includes memory cells, a multiplexer structure, a memory element, a bypass select multiplexer, and a control circuit. The memory cells implement a RAM driven by a write data input signal and a write enable signal. Each memory cell drives an input terminal of the multiplexer structure. Under the control of the write enable signal, a bypass select multiplexer selects either the write data input signal (in RAM mode) or the output terminal of the multiplexer structure (in another mode), and passes the selected signal to a memory element. Thus, when in RAM mode, write data is simultaneously written to a specified location in the RAM and to the memory element.

Abstract: A processor is specified for implementing actions for manipulating the fields of the packets of a communication protocol. A cluster specification is input specifying clusters of independent actions. A constraint specification is input of dependencies constraining performance of the actions, including a dependency between a first action from a first cluster and a second action from a second cluster. Each cluster is assigned to a stage of a dataflow pipeline of the processor, and the dependencies are satisfied by performing each stage in an order of the dataflow pipeline. The first action is transferred between the stages of the first and second clusters. A timeframe is scheduled for performing each action in each stage of the dataflow pipeline. The timeframe is scheduled for performing of the first and second actions in the stage of the second cluster in accordance with the dependencies. A specification of the dataflow pipeline is output.

Abstract: A computer-implemented method of verifying electrical isolation of portions of a circuit design for a programmable integrated circuit (IC) can include translating a circuit design into a circuit design bitstream specifying a plurality of regions, wherein the regions are to be isolated from one another. Routing resources of the programmable IC that are not used by the circuit design can be identified. A fence bitstream can be generated that specifies the unused routing resources. The circuit design bitstream can be compared with the fence bitstream. An indication of whether the plurality of regions of the programmable IC are isolated can be output according to the comparison.

Abstract: An integrated circuit device includes an output buffer having a capacitance circuit configurable in a slew rate configuration or a decoupling configuration. In the slew rate configuration, the capacitance circuit electrically couples a capacitor of the capacitance circuit in a feedback path for reducing a slew rate of a buffered output signal generated by the output buffer. In the decoupling configuration, the capacitance circuit electrically couples the capacitor between a power potential and a ground potential of the output buffer for increasing power noise immunity of the output buffer. The output buffer may have more than capacitance circuit, each of which is individually configurable into the slew rate configuration or the decoupling configuration.

Abstract: Method and apparatus for detecting a bit sequence in a data stream is described. In one example, a first memory is configured to process pairs of bit-patterns in the data stream to provide respective pairs of codes from a code table stored in said first memory. A second memory is configured to process pairs of codes from the first memory to provide combination codes from a combination code table stored in the second memory. A third memory is configured to generate detection data in response to a sequence of the combination codes output from the second memory. The first, second, and third memories may be dual-port synchronous memories, such as block random access memory embedded in an integrated circuit. The data stream may be a serial digital interface (SDI) data stream and the bit sequence may be a timing reference signal.

Abstract: A defect is automatically isolated in an integrated circuit device having programmable logic and interconnect circuits. A sequence of configurations is created to route data in a pattern through the programmable logic and interconnect circuits. Each configuration within the sequence is determined (e.g., generated or selected from a plurality of pre-generated configurations) as a function of output data from a prior configuration in the sequence. For each configuration in the sequence, the programmable logic and interconnect circuits are configured with the configuration and an automatic test instrument routes data in the pattern through the programmable logic and interconnect circuits. For each configuration in the sequence, the output data from the programmable logic and interconnect circuits is assessed. For each configuration in the sequence, the assessed output data isolates the defect to a portion of the pattern for the configuration that is within the portion for a prior configuration in the sequence.

Abstract: A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.

Abstract: Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.

Abstract: Embedded logic circuits in combination with a configurable logic resources on a common integrated circuit facilitates over-clocked operation of embedded, dual-port memory blocks. The implementation yields fully independent and simultaneous read/write access to the dual-port memory blocks from the configurable logic on each clock cycle of the configurable logic. Error detection/correction and data scrubbing is also facilitated by the embedded logic circuits, such that error detection/correction is completely transparent to the configurable logic, while data scrubbing is performed with minimal degradation to the memory access bandwidth of the configurable logic.

Abstract: An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells has a different critical ion track. Providing a four-plex of SEU-hardened memory cells, each with a different critical ion track, reduces the probability of a single ion upsetting adjacent memory cells.

Abstract: A method of evaluating a design under test (DUT) can include executing a testbench involving the DUT and, during execution of the testbench, estimating an amount of time needed to perform a first transaction with the device under test according to resolved variables. The method also can include setting a timer with the estimated amount of time needed to perform the first transaction and invoking the first transaction with the device under test. Responsive to expiration of the timer, an indication as to whether the first transaction completed execution can be provided.

Abstract: Method, apparatus, and computer readable medium for directed physical implementation of a circuit design for an integrated circuit is described. One aspect of the invention relates to implementing a circuit design for an integrated circuit. Matching elements between an original version of the circuit design and a modified version of the circuit design are identified. The original version includes an original implementation. The modified version is partially placed and routed to establish a guided implementation having guided placements and guided routes for the matching elements based on placements and routes from the original implementation. Actual timing characteristics for the guided placements and the guided routes are obtained. Since the routes in the guided implementation are fully implemented, actual timing characteristics can be exactly determined. Placement and routing in the modified implementation are completed using the actual timing characteristics.

Abstract: A method is provided for simulating a processor of network packets. A specification is input for the processor. The specification includes actions specifying a modification of the network packets by the processor. Each action includes a guard condition that enables and disables the action. First and second values of certain fields are determined for each action. The guard condition enables and disables the action respectively for the first and second values of the fields. The network packets are generated. For each field included in the guard conditions, a value of the field is selected for each generated network packet from the values of the field within the first and second values for the actions. The specification of the processor is translated into a simulator of the processor. The modification of the network packets is simulated in the simulator. A result of the modification is displayed on a user interface.

Abstract: An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.

Abstract: Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.

Abstract: A method of accessing a memory of a trellis decoder. The method comprises the steps of writing a first block of data associated with a trellis function to a first memory block; writing a second block of data associated with the trellis function to a second memory block; simultaneously writing a third block of data to a third memory block and reading the second block of data from the second memory block to generate training data; and simultaneously reading data to be decoded from the first memory block and writing a fourth block of data to the first memory block and generating training data associated with the third block of data. A circuit for accessing a memory of a trellis decoder is also described.

Abstract: A metal lid for packaging semiconductor chips is stamped to form a sloped sidewall with a set-back from the edge of a package substrate. After the metal lid is placed over the semiconductor chip, molding compound is formed around portions of the exposed perimeter of the package substrate and against the sloped sidewall of the lid. The molding compound securely attaches the lid to the package substrate, providing improved reliability to the lid-substrate joint. The lightweight lid also increases standoff when a solder ball-grid array is used to connect the packaged IC to a printed wiring board, improving the reliability of the ball-grid array connections.

Abstract: A method and system are disclosed. The system includes a trusted loader. The method includes downloading an IP core from a vendor to a target device. The IP core is received in an encrypted form at the target device, which can be, for example, a programmable logic device.

Abstract: A state machine circuit converts a first network packet into a second network packet according to modification actions from a textual language specification. Each modification action is either an insertion action inserting a data segment or a removal action removing a data segment. Each state corresponds to a pairing of a first data word from the first packet and a second data word from the second packet. Each state selects the data units of the second data word from the data segment of each insertion action and the data units of both the first and a prior data word. Each state specifies one or more next states including the state corresponding to the pairing of either the first or a next data word after the first data word in the first sequence and either the second or a next data word after the second data word in the second sequence.

Abstract: A computer-implemented method of balancing logic resource usage in a circuit design for a programmable integrated circuit (IC) includes determining that an assignment of elements of the circuit design to a first type of logic resource is unbalanced compared to an assignment of elements to an alternate type of logic resource. Binary variables are defined for circuit elements assigned to the first and alternate types of logic resources, where each binary variable indicates whether the associated circuit element is to be re-assigned to the first or alternate type of logic resource. Constraints are defined specifying relationships among selected variables. Values for the variables are obtained according to the constraints by minimizing a function dependent on a sum of the binary variables. Circuit elements are re-assigned to the first or alternate types of logic resources according to the values determined for the binary variables, and the circuit design is output.