Abstract: A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.

Abstract: A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.

Abstract: Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.

Abstract: Systems, methods, software, and techniques can be used to precharacterize a variety of prototype system designs. The prototype system designs can be defined at one or more levels of abstraction. The prototype designs are characterized using one or more electronic design automation tools to generate precharacterization data. Precharacterization data and associated prototype designs are used either directly or indirectly in the system level design process.

Abstract: Various approaches for displaying design data that implements an electronic design in lookup tables (LUTs) of a programmable logic device are disclosed. In one approach, a user is presented for selection at least two selectable modes for displaying a function performed by a LUT that is configurable with the design data to implement a function of the electronic design. The modes have associated, different formats for display of a function. In response to selection of an object that represents a first LUT having an assigned initialization value and in response to selection of one of the modes, the function performed by the first LUT, as defined by the initialization value, is displayed in the format associated with the selected mode.

Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, matching elements between a modified version of the circuit design and an implemented version of the circuit design are identified. Recommended placements for the matching elements are established based on placement information from the implemented version of the circuit design. An initial placement of the modified version of the circuit design is generated using the recommended placements. Timing-critical elements in the initial placement are identified. Locked placements for elements other than the timing-critical elements are established. An optimized placement of the modified version of the circuit design is generated using the locked placements.

Abstract: Integrated circuits, key components in thousands of products, frequently include thousands and even millions of microscopic transistors and other electrical components. Because of difficulties and costs of fabricating these circuits, circuit designers sometimes ask fabricators to produce skew lots for testing and predicting manufacturing yield. However, conventional skew lots for CMOS circuits, which are based on increasing or decreasing transistor transconductance, are not very useful in testing certain types of analog circuits, such as oscillators. Accordingly, the present inventors developed a new type of skew lot, based on increasing or decreasing gate-to-source capacitance of transistors, or more generally a transistor characteristic other than transconductance. This new type of skew lot is particularly suitable for simulating, testing, and/or making yield predictions for oscillators and other CMOS analog circuits.

Abstract: Apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.

Abstract: A method of oversampling a signal in an integrated circuit is disclosed. The method comprises receiving a reference clock signal; generating at least one delayed clock signal, each having a different phase; receiving an input data signal; generating at least one delayed data signal based upon the input data signal; and generating a plurality of phase-shifted output signals, each phase-shifted output signal being based upon a different combination of a clock signal and a data signal. A circuit for oversampling a signal in an integrated circuit is also disclosed.

Abstract: A method and apparatus is provided to enhance the power-up sequence for integrated circuits (ICs) that contain memory cells having single-ended data inputs with no local reset function. During a power-up sequence, the logic levels that are applied to the data, address, and power inputs of the memory cell are restricted to particular magnitudes by a power-on reset (POR) state machine. First, the data input of the memory cell is held to a logic low value while an address signal of the memory cell is allowed to be asserted to a logic high value in conjunction with activating a power supply that provides operational power to the IC. Next, the address input to the memory cell ramps up to full logic high value, while the regulated power supply to the memory cell array is held low. The regulated power supply then ramps up to an operational level to bias the memory cell into a known logic state.

Abstract: A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.

Abstract: A method of providing intensity correction for a video is disclosed. The method may comprise evaluating a portion of a frame of the video; determining a difference in intensity of a current block of the frame with the corresponding block of the previous frame; correcting all blocks of the frame with local intensity correction if a first set of parameters is met; and correcting the current block of the frame with both global intensity correction and local intensity correction if the first set of parameters is not met. An integrated circuit having a circuit for providing intensity correction for a video is also disclosed.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract: A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion; transferring data from the first portion to a second portion; outputting data at a second rate from the second portion, the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates.

Abstract: A through hole is formed in a circuit board (300) that has fibers (312) dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating (308) over the sputtered copper layer (306).

Abstract: An integrated circuit (100) has a transistor with an active gate structure 108 overlying an active diffusion area 112 formed in a semiconductor substrate 126. A dummy gate structure 110 is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer (130) overlying the transistor array produces stress in a channel region (107) of the transistor.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of the integrated circuit is configured to have a plurality of thread circuits and an interconnection topology amongst the plurality of thread circuits. Messages are concurrently processed using the plurality of thread circuits. Operation of at least one thread circuit of the plurality of thread circuits is controlled in accordance with control data received via the interconnection topology from at least one other thread circuit of the plurality of thread circuits.

Abstract: A system for authentication of information provided to an integrated circuit, a method for rights management of an integrated circuit, and a method for configuring a programmable logic device are described. A memory is coupled to a programmable logic device. The memory includes an array of memory cells and storage devices. The storage devices provide a first storage space and a second storage space. The first storage space is for storing a first identifier. The second storage space is for storing a second identifier, which is a transformation of the first identifier. The array of memory cells is for storing configuration information to configure programmable logic of the programmable logic device. The configuration information includes authentication logic information.

Abstract: A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator coupled to the plurality of receiver circuits, the bias current generator providing a bias voltage for each receiver circuit of the plurality of receiver circuits to mirror the current in the bias current generator in each of the receiver circuits. A method of reducing power consumption in input ports of an integrated circuit is also disclosed.

Abstract: An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.