Patents Assigned to Xilinx, Inc.
  • Method and apparatus for leakage current reduction
    Patent number: 7545177
    Abstract: Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: June 9, 2009
    Assignee: Xilinx, Inc.
    Inventors: Sean W. Kao, Tim Tuan, Arifur Rahman
  • Communication signal testing with a programmable logic device
    Patent number: 7546499
    Abstract: Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: June 9, 2009
    Assignee: XILINX, Inc.
    Inventors: Matthew S. Shafer, Bodhisattva Das, William C. Black, Scott Alan Irwin
  • Coprocessor interface controller
    Patent number: 7546441
    Abstract: A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the first frequency is a frequency of operation of the processor. The controller is coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, where the second frequency is a frequency of operation of the coprocessor which is slower than or equal to the first frequency. The controller is configured to operate at both the first frequency and the second frequency providing in part handshaking between the processor and the coprocessor such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: June 9, 2009
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Kathryn Story Purcell
  • Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems
    Patent number: 7546394
    Abstract: Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of configurable devices in the system and identify configuration data sets associated with the configurable devices. A system identifier value is generated and associated with the chain description data set. An archive is generated including the configuration data sets, chain description data set, and system identifier value.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: June 9, 2009
    Assignee: XILINX, Inc.
    Inventors: Neil G. Jacobson, Emigdio M. Flores, Jr., Sanjay Srivastava, Bin Dai, Sungnien Jerry Mao, Rosa M. Y. Chow, Pushpasheel Tawade
  • Solder ball assembly for a semiconductor device and method of fabricating same
    Patent number: 7545028
    Abstract: Solder ball assembly for a semiconductor device and method of fabricating the same is described. In one example, a solder mask is formed on a substrate having an aperture exposing at least a portion of a conductive pad of the substrate. A solder pillar is formed in the aperture and in electrical communication with the conductive pad. An insulating layer is formed on the solder mask exposing at least a portion of the solder pillar. The exposed portion of the solder pillar is removed to define a mounting surface. A solder ball is formed on the mounting surface in electrical communication with the solder pillar. The solder pillar may include high-temperature solder having a melting point higher than that of the solder ball.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: June 9, 2009
    Assignee: Xilinx, Inc.
    Inventor: Leilei Zhang
  • Validating partial reconfiguration of an integrated circuit
    Patent number: 7541833
    Abstract: Approaches for validating a configuration bitstream used for partially reconfiguring an ingrated circuit such as a programmable logic device (PLD) are disclosed. In one approach, the integrated circuit is configured with a first configuration bitstream that includes first bit values that produce an implementation of a static part of a design on the integrated circuit. Any differences between a bit value in a second configuration bitstream and a corresponding bit value of the implementation of the static part of the design are determined. The second configuration bitstream includes second bit values that produce an implementation of a reconfigurable part of the design on the integrated circuit. A first signal state is output in response to determining that there are no differences, and a second signal state is output in response to determining that there are differences.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 2, 2009
    Assignee: XILINX, Inc.
    Inventors: Stephen A. Neuendorffer, Brandon J. Blodget
  • Substrate coupled noise isolation for integrated circuits
    Patent number: 7541652
    Abstract: An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the noise sensitive circuit. The noise sensitive circuit is fabricated on the substrate. The first low impedance guard ring is fabricated on the substrate to at least partially surround the well-doped blocking ring, wherein the first low impedance guard ring is operably coupled to a first circuit ground, wherein impedance of the first low impedance guard ring is substantially less than impedance of the well-doped blocking ring.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: June 2, 2009
    Assignee: XILINX, Inc.
    Inventor: Firas N. Abughazaleh
  • Method of refreshing configuration data in an integrated circuit
    Patent number: 7539914
    Abstract: Configuration memory cells in an integrated circuit (IC) may be corrupted by cosmic radiation and other sources, causing improper operation of the IC. Reliability of an IC is improved by refreshing subsets, such as frames, of the configuration data according to a schedule that has one subset being refreshed more frequently than another subset. For each subset of the configuration data, a respective indicator is determined that indicates whether a subset of configuration memory of the IC requires refreshing with the subset of configuration data. The indicator may be a probability that corruption of the subset of configuration memory results in improper operation. A schedule for refreshing the subsets of configuration memory is generated from the indicators. The subsets of configuration memory are refreshed according to the schedule, with one subset being refreshed more frequently than another subset.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: May 26, 2009
    Assignee: Xilinx, Inc.
    Inventors: Prasanna Sundararajan, Jorn W. Janneck
  • Method of correcting errors stored in a memory array
    Patent number: 7539926
    Abstract: A method of correcting errors stored in a memory array is disclosed. According to various embodiments of the invention, the method comprises the steps of storing data in the memory array; reading back the data stored in the memory array; performing a check for errors on each frame of data in a first direction; and performing a check for errors in a second direction. The step of performing a check for errors may include a parity check or a cyclical redundancy check. Depending upon the number of errors detected in intersecting rows and columns, the state of cells of the memory array are selectively changed.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: May 26, 2009
    Assignee: Xilinx, Inc.
    Inventor: Austin H. Lesea
  • Automatic bug isolation in computer programming languages
    Patent number: 7539977
    Abstract: A method, system, and apparatus relating to automatically reducing an amount of code necessary for reproducing errors within programming language code is presented. The method can include identifying optional nodes of a hierarchical tree of programming language code, wherein each node of the tree corresponds to a type of programming language construct. A target node can be selected from the optional nodes. The method further can include excluding the target node and any sub-nodes of the target node from the programming language code, and determining whether the programming language code passes at least one test case.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: May 26, 2009
    Assignee: Xilinx, Inc.
    Inventor: Andrew W. Bloom
  • Circuit and method of transmitting a block of data
    Patent number: 7539923
    Abstract: A circuit for transmitting a block of data is disclosed. The circuit comprises a memory array having a plurality of memory locations coupled to receive data; a first data source coupled to the memory array, wherein data from the first data source is stored at sequential addressable memory locations of the plurality of memory locations on a first in, first out basis; a second data source coupled to the memory array, the second data source providing data to be stored in a predetermined memory location of the sequential addressable memory locations storing data from the second data source; and a selection circuit coupled to the first data source and the second data source for selecting data to be stored in the plurality of memory locations.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: May 26, 2009
    Assignee: Xilinx, Inc.
    Inventor: Tomai Knopp
  • Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system
    Patent number: 7539953
    Abstract: Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is specified. The at least one shared memory is associated with the at least one processor. A memory map associated with the at least one shared memory and a bus adapter for coupling the memory map to the at least one processor are automatically generated.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: May 26, 2009
    Assignee: Xilinx, Inc.
    Inventors: Shay Ping Seng, Jonathan B. Ballagh, Roger B. Milne, Bradley L. Taylor
  • Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor
    Patent number: 7539848
    Abstract: A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is configured according to configuration data provided to the integrated circuit device from an external memory and at least a portion of the logic fabric is configured as a configured processor to perform a first fixed logic function according to the configuration data. A fixed logic processor, a first auxiliary processing interface, a second fixed logic processor, a second auxiliary processing interface enable communication with the configured processor, wherein the configured processor remains configured to enable both the fixed logic processor and the second fixed logic processor to access the configured processor to perform the fixed logic function.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: May 26, 2009
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Douglass, Ahmad R. Ansari
  • Packet detector for a communication system
    Patent number: 7539241
    Abstract: Method and apparatus for packet detection is described. More particularly, a signal having sub-signals is received. The signal is quantized (“re-quantized”) to provide a quantized signal to processing units, where the quantized signal is a sequence of samples. A cross-correlation is done between the sequence of samples and a reference template, including totaling partial results from the processing units to provide a result. The result is a symbol timing synchronization responsive to the cross-correlation, which is provided in part by combining by addition or subtraction a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: May 26, 2009
    Assignee: XILINX, Inc.
    Inventor: Christopher H. Dick
  • Circuits providing greater depth and/or asymmetric access ports for first-in first-out memory circuits (FIFOs)
    Patent number: 7539789
    Abstract: Memory circuits that concatenate multiple FIFOs in parallel to increase the overall depth of the memory circuits. Asymmetric input and output ports can be provided by including a deserializer on the write interface of the memory circuit and/or a serializer on the read interface of the memory circuit. The deserializer disperses the data evenly across all FIFOs, minimizing the write-to-read latency. In some embodiments, at most two of the FIFOs are active at any given time, one being written and one being read, which reduces the overall power consumption of the memory circuit compared to known structures.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: May 26, 2009
    Assignee: Xilinx, Inc.
    Inventor: James E. Ogden
  • Probe card configured for interchangeable heads
    Patent number: 7535239
    Abstract: A probe card configured for interchangeable heads. In one example, a probe card includes a probe card circuit board and a substrate. The substrate includes a first interface coupled to the probe card circuit board and a second interface having a plurality of die patterns. The plurality of die patterns are arranged with respect to the substrate in a plurality of probe pin configurations for a respective plurality of probe heads.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: May 19, 2009
    Assignee: Xilinx, Inc.
    Inventors: Elvin P. Dang, Mohsen Hossein Mardi
  • Method and apparatus for a printed circuit board (PCB) embedded filter
    Patent number: 7535321
    Abstract: A printed circuit board (PCB) embedded filter is utilized to provide a low-pass filter characteristic using minimal lumped circuit elements. Microstrips extend on top layer of the PCB to conductive vias to form a first series connected inductive element, while microstrips extend from conductive vias to conductive vias to form a second series connected inductive element. Shunt capacitance is employed on a lower layer using striplines extending outwardly and symmetrically from conductive vias. An absorption circuit is implemented using microstrips on back layer of the PCB and capacitive plates on inner layers of the PCB. A surface mount resistor may be installed between pads to complete the absorption circuit.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: May 19, 2009
    Assignee: XILINX, Inc.
    Inventors: Michael J. Degerstrom, Matthew L. Bibee
  • Component naming
    Patent number: 7536377
    Abstract: Method and apparatus for component naming is described. Parameters (305) for a target component are obtained (201). The parameters (305) are hashed (202) to provide a hash value (203). The hash value (203) is used to construct a name (205) of the target component.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 19, 2009
    Assignee: Xilinx, Inc.
    Inventors: Roger B. Milne, Jeffrey D. Stroomer
  • Integrated circuit and method of routing a clock signal in an integrated circuit
    Patent number: 7536666
    Abstract: The various embodiments of the present invention relate to coupling clock signals between a plurality of data transceivers. According to one embodiment, a clock routing circuit having data transceivers comprises a clock bus interface and a first data transceiver coupled to the clock bus interface to receive a clock signal from the clock bus interface. A clock bus coupled to receive the clock signal enables the transfer of the clock signal to an adjacent data transceiver. According to other embodiments, various clock buses and interfaces enable routing clock signals between various circuits of the integrated circuit.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 19, 2009
    Assignee: Xilinx, Inc.
    Inventors: Thomas Anthony Lee, James P. Ross
  • Incremental placement during physical synthesis
    Patent number: 7536661
    Abstract: A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: May 19, 2009
    Assignee: XILINX, Inc.
    Inventors: Amit Singh, Kamal Chaudhary