Abstract: Systems, methods, software, and techniques can be used to provide and monitor simulation environments including one or more model components. A particular model component can have multiple different versions of the model component having varying levels of abstraction. Executing model components are monitored, and depending on certain performance characteristics, a model component can be replaced with a different version of that model component.

Abstract: Method and apparatus for digital frequency synthesis are described. A frequency synthesizer has an accumulator, an adder, and a predictive filter. The adder is configured to subtract a predicted error from a phase profile signal. A quantized version of the phase profile signal is separated from an error portion thereof. The predictive filter, set for a fraction of a sample frequency bandwidth, is coupled to receive the error portion for generation of a next predicted error. A storage device has digital representations of sinusoidal signals accessible responsive to the quantized version of the phase profile signal. A digital-to-analog converter is coupled to receive a digital representation of a sinusoidal signal obtained from the storage device to provide an analog sinusoidal signal. An anti-imaging filter is coupled to receive the analog sinusoidal signal and configured to filter out noise.

Abstract: A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow prior to a selected task that does not recognize a constraint, wherein the preprocessing task introduces a modification into the circuit design according to the constraint. The circuit design including the modification can be processed through the selected task of the CAD flow. A reversal task can also be inserted into the CAD flow, wherein the reversal task removes the modification introduced into the circuit design by the preprocessing task. The method further can include processing the circuit design through at least one other task of the CAD flow and outputting the processed circuit design.

Abstract: A method of generating interleaver addresses in a circuit for decoding data is disclosed. The method comprises the steps of receiving a data stream having a plurality of data blocks, each block having N bits; dividing each data block of the plurality of data blocks into m windows, each window comprising N/m bits; and calculating an interleaver address for each window as a function of modulo N/m. A circuit for generating an interleaver address in a circuit for decoding data is also disclosed.

Abstract: Various embodiments of the present invention relate to a device for testing an integrated circuit. According to one embodiment, the device comprises a first connector coupled to receive a device under test and a second connector coupled to receive compressed test data by way of test equipment. The device also comprises a decompressor coupled to receive compressed test data, and provided decompressed test data to the device under test. Embodiments implementing two different clocks to improve the speed of testing integrated circuits are also disclosed. Various methods for coupling test signals to a device under test are also disclosed.

Abstract: Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).

Abstract: A method for customization of the software of an FPGA-based SoC includes the steps of selecting (380) a system component used for customizing the FPGA-based SoC, configuring (382) the selected system component with parameters for use with the FPGA-based SoC and propagating (384) the parameters used to configure the selected system component to peer system components. The method further includes the step of configuring (388) the peer system components using the propagated parameters during customization of the FPGA-based SoC and creating (401) a software interface to the selected system components and to the peer system components.

Abstract: According to one aspect of the invention, a method of interleaving data for enabling data coding in a communication network is disclosed, the method including storing parameters required to output address sequences for a matrix, receiving a block size associated with a block of data at a circuit for interleaving data, outputting parameters associated with the stored parameters based upon the block size, and producing an address sequence using the parameters. A circuit for interleaving data for data coding in a communication network is also disclosed. The circuit includes a lookup table storing parameters required to output address sequences for a matrix. A search coupled to the lookup table receives a clock size associated with a matrix and outputs parameters based upon the block size. A computation circuit coupled to receive the parameters outputs an address sequence using the parameters.

Abstract: A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.

Abstract: Generation of a random sequence using alpha particle emissions is described. A device includes memory cells, an alpha particle emitter, and read circuitry. The memory cells are sensitive to alpha particle emissions. The alpha particle emitter is proximate to the memory cells for changing state of one or more bits of the memory cells within a period of time. The read circuitry is coupled to the memory cells and configured to periodically issue a read command to periodically read the memory cells.

Abstract: Methods of implementing state machines using embedded processors. The designer specifies the logical footprint of the state machine in a formalism that can be transformed into hardware. This approach decouples the designer from the design, so that a state machine can be moved between embedded processors (e.g., between a hard processor and a soft processor), without any modifications to the code. One or more source-to-source transformations can be performed to improve the run-time performance of the state machine. These transformations can include the insertion of one or more jump addresses directly into the code, bypassing the standard lookup table approach for memory addressing, and consequently speeding up the execution of the code. The jump addresses can include, for example, a jump address for the start of each state machine, and/or a jump address for each state within the state machines.

Abstract: A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

Abstract: A method of calculating power usage of a lookup table (LUT) implemented on a programmable logic device can include determining input power usage of the LUT and determining output power usage of the LUT. The method further can include determining internal power usage of the LUT. Data rates, LUT configuration, and node capacitance information can be used in determining input, output, and internal power. A measure of power usage for the entire LUT can be provided by summing the input power usage, the output power usage, and the internal power usage.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.

Abstract: A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

Abstract: Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

Abstract: An interrupt controller efficiently manages execution of tasks by a multiprocessor computing system. The interrupt controller has inputs for receiving service requests for invoking service routines. The service routines have higher priorities than the tasks executed on the processors. Associated with each processor is a register for storing the priority of the task executing on the processor. A comparator coupled to the processors determines the processor executing the task having a lower priority among the priorities of the tasks executing on the processors. For each service request received, a distributor generates an interrupt request for invoking the service routine of the service request on the processor with the lower priority. The register with the lower priority is set to the higher priority of the service routine in response to the interrupt request. For each processor, the interrupt controller has an output for transmitting the interrupt request to the processor.

Abstract: An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.

Abstract: Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.

Abstract: Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.