Patents Assigned to Xilinx, Inc.
  • END-TO-END QUALITY-OF-SERVICE IN A NETWORK-ON-CHIP
    Publication number: 20190238453
    Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Applicant: Xilinx, Inc.
    Inventors: Ian A. Swarbrick, Ygal Arbel, Millind Mittal, Sagheer Ahmad
  • ADC based receiver
    Patent number: 10367666
    Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventors: Hongtao Zhang, Yohan Frans, Geoffrey Zhang
  • Timing closure of circuit designs for integrated circuits
    Patent number: 10366201
    Abstract: Closing timing for a circuit design can include displaying, using a display device, a first region having a plurality of controls corresponding to a plurality of data sets generated at different times during a phase of a design flow for a circuit design, wherein each control selects a data set associated with the control, and displaying, using the display device, a second region configured to display a list of critical paths for data sets selected from the first region using one of the plurality of controls. Closing timing further can include displaying, using the display device, a third region configured to display a representation of a target integrated circuit including layouts for the critical paths of the list for implementations of the circuit design specified by the selected data sets.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventors: Aaron Ng, Sridhar Krishnamurthy, Grigor S. Gasparyan
  • Single event upset (SEU) mitigation for FinFET technology using fin topology
    Patent number: 10366999
    Abstract: Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventor: Pierre Maillard
  • Pusher pin having a non-electrically conductive portion
    Patent number: 10367279
    Abstract: An electrically insulative pusher pin is disclosed. In one example, an electrically insulative pusher pin includes a first plunger member, a second plunger member, and a spring. The first plunger member has a first end and an exposed second end. The second plunger member has a first end and an exposed second end. The second plunger member is movable relative to the first plunger member, where the exposed second ends of the first and second plunger members defining a length of the pusher pin. The spring disposed between the first ends of the first and second plunger members and biases the exposed second end of the first plunger member away from the exposed second end of the second plunger member. An electrically insulative path is defined between the exposed second end of the first plunger member and the exposed second end of the second plunger member through the pusher pin.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventor: Mohsen H. Mardi
  • Optical driver with asymmetric pre-emphasis
    Patent number: 10367591
    Abstract: An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The inductive circuit may include an L output terminal to output an output signal, a P coil coupled between the P output terminal and the L output terminal, and an N coil coupled between the N output terminal and the L output terminal.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventor: Mayank Raj
  • Partitioning memory blocks for reducing dynamic power consumption
    Patent number: 10366001
    Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventors: Nithin Kumar Guggilla, Chaithanya Dudha, Krishna Garlapati, Chun Zhang, Fan Zhang, Anup Kumar Sultania
  • ISOLATION ENHANCEMENT WITH ON-DIE SLOT-LINE ON POWER/GROUND GRID STRUCTURE
    Publication number: 20190229113
    Abstract: Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 25, 2019
    Applicant: Xilinx, Inc.
    Inventors: Zhaoyin D. Wu, Parag Upadhyaya, Kun-Yung Chang
  • Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC
    Patent number: 10354733
    Abstract: Methods and apparatus are described for partitioning and reordering block-based matrix multiplications for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). By preloading and hierarchically caching the blocks, examples of the present disclosure reduce the double data rate (DDR) memory intake bandwidth for software-defined GEMM accelerators.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 16, 2019
    Assignee: XILINX, INC.
    Inventors: Jindrich Zejda, Elliott Delaye, Ashish Sirasao, Yongjun Wu, Aaron Ng
  • Programmable digital sigma delta modulator
    Patent number: 10348310
    Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Karim M. Megawer, Parag Upadhyaya, Didem Z. Turker Melek, Zhaoyin D. Wu
  • Memory arrangement for tensor data
    Patent number: 10346093
    Abstract: Disclosed circuitry includes RAM circuits, a memory controller, and an array of processing circuits. Each RAM circuit includes a read port and a write port. The memory controller accesses tensor data arranged in banks of tensor buffers in the RAM circuits. The memory controller is coupled to each read port by shared read control signal lines and to each write port by shared write control signal lines. The memory controller generates read control and write control signals for accessing different ones of the tensor buffers at different times. The array of processing circuits is coupled to one of the RAM circuits. The array includes multiple rows and multiple of columns of processing circuits for performing tensor operations on the tensor data. The processing circuits in each row in each array of processing circuits are coupled to input the same tensor data.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Ephrem C. Wu, Xiaoqian Zhang, David Berman
  • System and method for transmitter
    Patent number: 10348290
    Abstract: A transmitter includes a predriver circuit configured to perform a first equalization process to compensate jitter caused by the predriver circuit. The predriver circuit includes a first path having a first driving strength and configured to generate a first path output signal by applying a first delay to a predriver input signal. The predriver circuit includes a second path having a second driving strength less than the first driving strength and configured to generate a second path output signal by applying a second delay to the predriver input signal. A summing node is configured to combine the first path output signal and the second path output signal to provide a summing node output signal. A driver circuit coupled to the predriver circuit is configured to generate a driver output signal based on the summing node output signal and drive the driver output signal to a receiver through a channel.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Hongtao Zhang, Yohan Frans
  • Inclusion and configuration of a transaction converter circuit block within an integrated circuit
    Patent number: 10346572
    Abstract: A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Kyle Corbett, Khang K. Dao
  • Inline ECC function for system-on-chip
    Patent number: 10346346
    Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Ian A. Swarbrick, Sagheer Ahmad
  • Circuit for and method of implementing a bursty clock and data recovery circuit using an eyescan detection circuit
    Patent number: 10348312
    Abstract: A circuit for receiving data is described. The circuit comprises a phase detector circuit comprising a detector having a first input configured to receive a sum of an oscillator phase and a phase error, and a second input coupled to an output of a first sample selector; a second sample selector having an input coupled to receive the input data and generate output data; and an eye detection circuit comprising a third sample selector having an input coupled to receive the input data and a comparator for comparing outputs of the second sample selector and the third sample selector to determine how much an eye is open for a plurality of channels. A method of implementing a receiver is also described.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Paolo Novellini, Antonello Di Fresco
  • OPTICAL DRIVER WITH ASYMMETRIC PRE-EMPHASIS
    Publication number: 20190207687
    Abstract: An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The inductive circuit may include an L output terminal to output an output signal, a P coil coupled between the P output terminal and the L output terminal, and an N coil coupled between the N output terminal and the L output terminal.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 4, 2019
    Applicant: Xilinx, Inc.
    Inventor: Mayank Raj
  • Configurable latch circuit
    Patent number: 10340898
    Abstract: The disclosed pulsed latched circuitry includes first and second latch circuits. The first and second latch circuits can be provided with additional logic circuit components to permit them to be operated as a flip-flop circuit, or as a FIFO circuit with a depth of two.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 2, 2019
    Assignee: XILINX, INC.
    Inventor: Ilya K. Ganusov
  • INLINE ECC FUNCTION FOR SYSTEM-ON-CHIP
    Publication number: 20190196901
    Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Applicant: Xilinx, Inc.
    Inventors: Ygal Arbel, Ian A. Swarbrick, Sagheer Ahmad
  • Systems and methods for providing capacitor structures in an integrated circuit
    Patent number: 10332885
    Abstract: A capacitor includes a cell array including a plurality of cells and a fine tuning cell electrically coupled to the cell array by a first bus and a second bus. Each cell of the cell array includes a first number of fingers electrically coupled to the first and second bus, and a second number of fingers electrically coupled to the first and second bus. The fine tuning cell includes a third number of fingers electrically coupled to the first and second bus, and a fourth number of fingers electrically coupled to the first and second bus. The directional alignment of the first and second number of fingers is generally perpendicular, the directional alignment of the third and fourth number of fingers is generally perpendicular, and the second number of fingers is different than the fourth number of fingers.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventor: Jing Jing
  • Loop optimization for implementing circuit designs in hardware
    Patent number: 10331836
    Abstract: Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventors: Anup Hosangadi, Sumanta Datta, Aman Gayasen, Ashish Sirasao