Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.

Abstract: A method, non-transitory computer readable medium, and apparatus for preventing accelerated aging of a physically unclonable function (PUF) circuit are disclosed. For example, the method monitors an environmental condition associated with the physically unclonable function circuit, detects a change in the environmental condition associated with the physically unclonable function circuit, and, in response to the change in the environmental condition, implements a security function for preventing the accelerated aging of the physically unclonable function circuit.

Abstract: A memory array having improved radiation immunity is described. The memory array comprises a plurality of memory elements, each memory element having an p-type transistor formed in an n-type region; and a plurality of p-wells, each p-well having an n-type transistor coupled to a corresponding p-type transistor to form a memory element of the plurality of memory elements; wherein each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor and associated with at least two adjacent memory elements. A method of implementing a memory array is also described.

Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.

Abstract: An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.

Abstract: Approaches for recovery of media datagrams are disclosed. Media datagrams, row forward error correction (FEC) datagrams, and column FEC datagrams are received. The media datagrams are logically arranged in rows and columns, each row and column having a corresponding FEC datagram. First, second, and third bitmaps are constructed to respectively indicate availability of media datagrams, row FEC datagrams, and column FEC datagrams. A recoverable media datagram is located in the plurality of media datagrams and is recovered. In response to recovering a datagram using a row FEC datagram, the column having the datagram is checked using the bitmaps to determine if another datagram in the column is recoverable. In response to recovering a datagram using a column FEC datagram, the row having the recovered media datagram is checked to determine if another datagram in the row is recoverable.

Abstract: A method and system of preventing data imprinting. The data includes a payload and a token that may be stored in a memory. The token provides information about the payload format and determines how that payload may be interpreted. The data field may be corrected and read into a device or may be converted and then written back to the memory.

Abstract: An encoder block to receive input data has a KR-Matrix block. The KR-Matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n?1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n?1) parity bits to generate an (n) parity bit.

Abstract: An embodiment of an apparatus for encoding. For this embodiment of the apparatus, an encoder block is coupled to receive input data. The encoder block has an R-matrix block. The R-matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n?1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n?1) parity bits to generate an (n) parity bit 9-to-7.

Abstract: An integrated circuit that equalizes delay across process corners. A delay equalizer circuit is used to adjust and maintain a relatively constant delay across different process corners. The delay equalizer circuit includes a process monitor and a delay compensator circuit coupled to the process monitor. The process monitor may output a compensating bias voltage for a pMOS transistor and a compensating bias voltage for an nMOS transistor. The compensating bias voltages may be used to regulate and maintain a relatively constant delay through the delay compensator circuit across varying process corners.

Abstract: The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses incoming data to measure and to compensate the skew between two or more free running oversamplers (e.g., SerDes), without the need for any hardware design requirement relating to the precision of the relative skew of the oversamplers.

Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract: An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.

Abstract: A method and apparatus for authenticating a bitstream used to configure programmable devices are described. In an example, the bitstream is received via a configuration port of the programmable device, the bitstream including instructions for programming configuration registers of the programmable device and at least one embedded message authentication code (MAC). At least a portion of the instructions is initially stored in a memory of the programmable device without programming the configuration registers. At least one actual MAC is computed based on the bitstream using a hash algorithm. The at least one actual MAC is compared with the at least one embedded MAC, respectively. Each instruction stored in the memory is executed to program the configuration registers until any one of the at least one actual MAC is not the same as a corresponding one of the at least one embedded MAC, after which any remaining instructions in the memory are not executed.

Abstract: Reducing jitter in a circuit design includes selecting a plurality of circuit elements of a circuit design clocked using a first clock signal and assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion. The circuit elements assigned to a first group of the plurality of groups are clocked using the first clock signal. The circuit elements assigned to a second group of the plurality of groups are clocked using a second clock signal different from the first clock signal.

Abstract: An embodiment of an interposer is disclosed. For this embodiment of the interposer, a first circuit portion is created responsive to a first printing region. A second circuit portion is created responsive to a second printing region. The interposer has at least one of: (a) a length dimension greater than a maximum reticle length dimension, and (b) a width dimension greater than a maximum reticle width dimension.

Abstract: Routing a multi-fanout net includes selecting a driver component of the multi-fanout net of a circuit design, wherein the circuit design is specified programmatically, and determining a plurality of targets of the driver component. A source wave is created at each of a plurality of nodes of the driver component. One target is assigned to each source wave. Each source wave is expanded.

Abstract: A device and method for clock and data recovery are disclosed. For example, an integrated circuit comprises a first branch for recovering a clock signal from an input signal. The first branch includes a phase and frequency detector for detecting a phase and a frequency of the clock signal and a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector. The integrated circuit also includes a second branch for recovering a data signal from the input signal. The second branch includes a pre-settable numerically controlled oscillator that is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator. The second branch also includes a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering the data signal.

Abstract: In one embodiment, a circuit for FEC decoding includes first and second syndrome calculation circuits, configured to calculate FEC syndromes for rows and columns of symbols in a de-interleaved format, respectively. A decoding circuit is configured to arrange the symbols into windows. Each window includes a plurality of sequential rows and sequential columns of the symbols in the de-interleaved format. The decoding circuit is configured to place N of the windows in a group and perform M decoding iterations of the windows in the group. In each decoding iteration, the decoding circuit performs FEC decoding of rows of each of the windows in the group followed by FEC decoding of columns of each of the windows in the group.