Abstract: According to an embodiment of present disclosure, a method of forming a carbon film on a substrate to be processed is provided. The method includes loading a substrate to be processed with a carbon film formed thereon into a processing chamber of a film forming apparatus (Process 1), and thermally decomposing a hydrocarbon-based carbon source gas in the processing chamber to form a carbon film on the substrate to be processed (Process 2). In Process 2, a film forming temperature of the carbon film is set to a temperature less than a thermal decomposition temperature of a simple substance of the hydrocarbon-based carbon source gas without plasma assistance, the hydrocarbon-based carbon source gas and a thermal decomposition temperature drop gas containing a halogen element are introduced into the processing chamber, and a non-plasma thermal CVD method is performed.

Abstract: A wafer processing method divides a wafer into individual devices along crossing streets formed on the front side of the wafer. The wafer has a substrate and a functional layer formed on the front side of the substrate. The individual devices are formed from the functional layer and are partitioned by the streets. A laser beam is applied along the streets from the front side of the functional layer to thereby remove the functional layer along the streets. A resist film is formed on the front side of the functional layer except on each street. The substrate of the wafer is plasma-etched along each street where the functional layer is absent to the depth corresponding to the finished thickness of each device, thereby forming a division groove along each street and also etching off a modified layer formed on the opposite sides of each street.

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Abstract: To provide a method of efficiently manufacturing an organic light-emitting element with excellent light-emitting characteristics by application, the method includes: preparing ink and filling an inkjet device having an ink ejection nozzle with the ink; preparing a substrate having a base layer including a first electrode; and positioning the inkjet device above the substrate, and causing the inkjet device to eject a drop of the ink onto the base layer, wherein, in the preparation of the ink, a value Z denoting a reciprocal of the Ohnesorge number Oh determined by density ? (g/dm3), surface tension ? (mN/m), and viscosity ? (mPa·s) of the ink and a diameter r (mm) of the ink ejection nozzle satisfies Formula 1, in the ejection of the drop of the ink, speed V (m/s) of the ejected drop satisfies Formula 2, and the value Z and the speed V (m/s) satisfy Formula 3.

Abstract: Processes for forming an actuator having a curved piezoelectric membrane are disclosed. The processes utilize a profile-transferring substrate having a curved surface surrounded by a planar surface to form the curved piezoelectric membrane. The piezoelectric material used for the piezoelectric actuator is deposited on at least the curved surface of the profile-transferring substrate before the profile-transferring substrate is removed from the underside of the curved piezoelectric membrane. The resulting curved piezoelectric membrane includes grain structures that are columnar and aligned, and all or substantially all of the columnar grains are locally perpendicular to the curved surface of the piezoelectric membrane.

Abstract: A pixel structure of display panel includes a first thin film transistor device, a second thin film transistor device, a first passivation layer, a common electrode, a second passivation layer, a first pixel electrode and a second pixel electrode. The first passivation layer has a first opening partially exposing a first drain electrode of the first thin film transistor device and a second drain electrode of the second thin film transistor device. The common electrode has a second opening partially exposing the first drain electrode and the second drain electrode. The second passivation layer has a third opening partially exposing the first drain electrode and the second drain electrode. The first pixel electrode is electrically connected to the first drain electrode through the third opening, the second opening and the first opening, and the second pixel electrode is electrically connected to the second drain electrode through the third opening, the second opening and the first opening.

Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.

Abstract: The present invention relates to a silicon solar cell module comprising electrodes formed from conductive paste. In the invention, front electrode finger lines and front electrode bus bars are separately formed. The front electrode finger lines are formed by printing a silver paste and calcining the printed silver paste at high temperature, and rear electrode bus bars and front electrode bus bars are formed from an inexpensive lower-temperature conductive paste including a buffer and a curing agent having reducing power, whereby the expensive silver paste is replaced with the inexpensive low-temperature conductive paste, thereby reducing the production cost.

Abstract: An organic electroluminescence display panel comprises a first substrate, a second substrate assembled to the first substrate, an organic light-emitting layer positioned between the first and second substrates, a sealant positioned between the first and second substrates, a varying pattern zone, and supplemental pattern zone. The second substrate comprises a sealant dispensing area, a metal region, and a non-metal region adjacent to the metal region. The metal region includes plural traces. The sealant is formed in the sealant dispensing area of the second substrate. The varying pattern zone is formed at one of the traces of the metal region, and is corresponding to the sealant dispensing area. The varying pattern zone comprises plural conductive portions. The supplemental pattern zone comprising plural supplemental conductive portions is formed at the non-metal region. A width of the conductive portions is larger than a width of the supplemental conductive portions.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a gate structure on the first region, in which the gate structure comprises a first hard mask and a second hard mask thereon; forming a first mask layer on the first region and the second region; removing part of the first mask layer; removing the second hard mask; forming a second mask layer on the first region and the second region; removing part of the second mask layer; and removing the first hard mask.

Abstract: A method for forming a silicon germanium oxide thin film on a substrate in a reaction space may be performed using an atomic layer deposition (ALD) process. The process may include at least one cycle comprising a germanium oxide deposition sub-cycle and a silicon oxide deposition sub-cycle. The germanium oxide deposition sub-cycle may include contacting the substrate with a germanium reactant, removing excess germanium reactant, and contacting the substrate with a first oxygen reactant. The silicon oxide deposition sub-cycle may include contacting the substrate with a silicon reactant, removing excess silicon reactant, and contacting the substrate with a second oxygen reactant. The films of the present disclosure exhibit desirable etch rates relative to thermal oxide. Depending on the films' composition, the etch rates may be higher or lower than the etch rates of thermal oxide.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can prepare a substrate unit including a base substrate, an intermediate crystal layer, and a first mask layer. The intermediate crystal layer has a major surface having a first region, a second region, and a first intermediate region. The first mask layer is provided on the first intermediate region. The method can implement a first growth to grow a first lower layer on the first region and grow a second lower layer on the second region. The first and second lower layers include a semiconductor crystal. The method can implement a second growth to grow a second upper layer while growing a first upper layer to cover the first mask layer with the first and second upper layers. The method can implement cooling to separate the first and second upper layers.

Abstract: A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.

Abstract: Temporary substrates may include a bonding surface prepared for receiving an additional substrate that will transfer a thin layer. Such substrates may include a principal part or support and a surface layer thereon with the surface layer having a plurality of inserts therein. The inserts are made of a material having a coefficient of thermal expansion that is significantly different from that of the material constituting the surface layer. Processing methods for transferring a selected portion of an original substrate may involve such temporary substrates and productions methods may produce such temporary substrates.

Abstract: Methods for plasma treatment of films to remove impurities are disclosed herein. Methods for removing impurities can include positioning a substrate with a barrier layer in a processing chamber, the barrier layer comprising a barrier metal and one or more impurities, maintaining the substrate at a bias, creating a plasma comprising a treatment gas, the treatment gas comprising an inert gas, delivering the treatment gas to the substrate to reduce the ratio of one or more impurities in the barrier layer, and reacting a deposition gas comprising a metal halide and hydrogen-containing gas to deposit a bulk metal layer on the barrier layer. The methods can further include the use of diborane to create selective nucleation in features over surface regions of the substrate.

Abstract: The present technology includes: bonding a device formation side of a first substrate having a first device and a device formation side of a second substrate having a second device in opposition to each other; forming a protective film on at least an edge of the second substrate having the second device; and reducing a thickness of the first substrate.

Abstract: An epitaxial-deposition composite substrate, of more than about 50 mm diameter, in which a nitride-compound semiconductor first substrate is bonded together with a second substrate of either identical or different material. The first substrate is ion-implanted, and on its nitrogen-face side is coated with a special film of thickness within a predetermined range. On a bonding side of the second substrate a special coating of thickness within the predetermined range is formed. The join created by the coated nitrogen-face side of the first substrate being bonded to the coated bonding side of the second substrate occupies at least 90% of the surface area where the two substrates meet.

Abstract: A non-volatile semiconductor memory device has a semiconductor substrate, an element isolation region disposed in a surface of the semiconductor substrate, a well region disposed along one principal surface of the semiconductor substrate, source and drain regions arranged in the well region, a gate oxide film arranged on the surface of the semiconductor substrate between the source region and the drain region, a floating gate disposed on the gate oxide film, and an insulating film disposed on a surface of the floating gate. A control gate is capacitively coupled to the floating gate disposed through intermediation of the insulating film. A resistive element is serially connected to the control gate. Write characteristics of the non-volatile semiconductor memory device are improved as a result of a delay effect of the resistive element serially connected to the control gate.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.