Abstract: A switching device includes a semiconductor substrate having a first element range and an ineffective range. First trenches extend in a first direction across the first element range and the ineffective range. Second trenches are provided in each inter-trench region within the first element range and are not provided within the ineffective range. A gate electrode is disposed in the trenches. No contact hole is provided in an interlayer insulating film within the ineffective range. The first metal layer covers the interlayer insulating film. The insulating protective film covers a portion of the first metal layer on its outer peripheral side within the ineffective range. The second metal region is in contact with the first metal layer within an opening of the insulating protective film, and is in contact with a side surface of the opening.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an anti-punch through implant (APT) region formed in the fin structure and a barrier layer formed on the APT region. The barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion. The FinFET device structure further includes an epitaxial layer formed on the barrier layer.

Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is conformally formed to cover the sidewalls of the spacers, the exposed portion of the semiconductor fin and the exposed portions of the insulators, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed on the second dielectric layer and between the spacers.

Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.

Abstract: The light emitting display device comprises: a substrate including a plurality of pixels that are arranged in a first direction and a second direction that crosses the first direction; a first electrode for each pixel on the substrate; a pixel defining layer on the substrate, the pixel defining layer having an opening for exposing the first electrode; a hole injection layer on the first electrode; a lyophilic pattern extending on the hole injection layer to cover the first electrode and the pixel defining layer that are on a same line in the first direction, and extending up to an outer region of outermost pixels of the plurality of pixels in the first direction; a hole transport layer on the lyophilic pattern; a light emitting layer on the hole transport layer; and a second electrode on the light emitting layer, wherein the lyophilic pattern includes a first lyophilic pattern having a plurality of grooves on one end portion thereof in the first direction and a second lyophilic pattern having a plurality of g

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes: (a) accommodating a substrate having a plurality of carbon-containing films protruding from a surface of the substrate; (b) forming a silicon-containing film on a surface of the plurality of carbon-containing films and a surface of the substrate by supplying a silicon-containing gas to the substrate; (c) forming a silicon/oxygen-containing film by supplying a first plasma of an oxygen-containing gas to the substrate; and (d) forming a silicon oxide film by supplying a second plasma of the oxygen-containing gas to the substrate after performing (c).

Abstract: An array substrate is provided. The array substrate includes a base substrate, and a buffer layer, a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer, a source/drain metal layer and a pixel electrode layer that are subsequently formed on the base substrate, and a common electrode layer formed between the base substrate and the buffer layer. The array substrate has an increased storage capacitance and an improved maintenance ratio of pixel voltage, suppresses the unfavorable phenomenon like flicker of the display device. A method for manufacturing an array substrate and a display device including such an array substrate are also provided.

Abstract: A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions.

Abstract: A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.

Abstract: A mask frame assembly manufactured via an extension-welding process on a stage, the mask frame assembly includes: a mask frame disposed on a stage, the mask frame including a first frame and a second frame having a first length, and a third frame and a fourth frame having a second length, the second length less than the first length. The mask frame assembly also includes a mask having respective ends welded and combined onto the first frame and the second frame. The first frame and the second frame include a slot disposed toward the stage, and at least portions of the first frame and the second frame corresponding to the slot are not in contact with the stage. The third frame and the fourth frame and the stage are in contact with the stage.

Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a light emitting layer; and a phosphor layer provided on the semiconductor layer. The phosphor layer includes a plurality of phosphors, ?0.05<A×(AR)+B×(Np)+C<0.05 being satisfied for ?0.149055?(3×0.011797)?constant A??0.149055+(3×0.011797), ?0.000192?(3×0.00002461)?constant B??0.000192+(3×0.00002461), and 0.0818492?(3×0.005708)?constant C?0.0818492+(3×0.005708). AR is a ratio of a thickness of the phosphor layer to a width of the phosphor layer, and Np is a number of the plurality of phosphors.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

Abstract: A Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region.

Abstract: A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

Abstract: In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material.

Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

Abstract: A semiconductor device includes a control gate electrode and a memory gate electrode which are formed over the main surface of a semiconductor substrate in a memory cell region, and a first electrode and a second electrode which are formed over the main surface of the semiconductor substrate in a shunt region. The first electrode is formed integrally with the control gate electrode, and the second electrode is formed integrally with the memory gate electrode. The second electrode includes a first section formed along the side wall of the first electrode, and a second section extending along the main surface of the semiconductor substrate. Also, the height of the upper surface of the first electrode with respect to the main surface of the semiconductor substrate is generally same to the height of the upper surface of the first section of the second electrode.

Abstract: A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.

Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.