Abstract: A junction is formed by the establishment of first and second adjacent conductivity regions having a transition therebetween from wide (2D) to narrow (1D) with respect to the electron wavelength at the Fermi level. The electrons in the wide region can be propagated at any of a continuum of energies in two dimensions while, in the narrow region, allowable energies become quantized, forming a potential barrier similar to a junction in a tunnel diode. The junction formed in this manner exhibits a Coulomb blockade effect and can be made to operate alternatively as an extremely small capacitance and a conductance to sequentially transfer single electrons, thus forming a Coulomb blockade gate. The Coulomb blockade gate can be used in an oscillator or in digital counting and memory applications.

Abstract: An improved Electrostatic Discharge (ESD) protection device for use in the electrostatic discharge testing of an integrated circuit (IC). In accordance with the invention, a p-n junction is formed beneath a polysilicon resistor, with a metal oxide layer separating the resistor and the p-n junction. The p-n junction is formed by positioning a semiconductor well having a first polarity between the metal oxide and a semiconductor substrate having a second polarity. The invention reduces the electrostatic potential across the metal oxide layer, which could otherwise result in damage to the metal oxide during ESD testing of the IC. In a preferred embodiment, the invention includes a switch, such as a transistor, between the well and ground, for allowing the well to float freely during normal circuit operation (to reduce noise) and for fixing the well at a fixed potential during ESD testing.

Abstract: A substrate applicable to be used in a multichip module including a plurality of integrated circuits. The substrate includes a series of interrelated metal layers, ceramic layers and lattice structures formed by the ceramic layers. The metal layers provide ground planes, power planes and interconnects for the integrated circuit. The lattice structure consists of a series of ceramic regions separating the ceramic layers such that the majority of the lattice structure is air in order to reduce the effective dielectric constant of the substrate.

Abstract: A read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines and column lines are arrayed alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the HIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and a third selection switch are provided for selecting the bit line and the column line of the group, respectively.

Abstract: A nonvolatile semiconductor memory is comprised of a semiconductor substrate composed of N-type silicon, a pair of source and drain regions having opposite electroconductivity to that of the semiconductor substrate and being formed in a surface region of the semiconductor substrate in spaced relation to each other to define therebetween a channel region, a gate insulating film formed on the channel region, a floating gate electrode formed on the gate insulating film over the channel region and composed of N-type polysilicon, and an insulating layer formed to cover the floating gate electrode. The floating gate electrode is composed of the N-type polysilicon effective to reduce the thickness of adjacent gate insulating film below 500 .ANG. to thereby significantly micronize the dimension of memory.

Abstract: A high-frequency semiconductor hybrid integrated circuit device with desirable high-frequency properties and reduced floating capacitance that is easily manufactured at lower cost with reduced labor. A coupling dielectric substrate bearing conducting films as a circuit pattern is joined to a main dielectric substrate mounted on a heat radiating plate and bearing elements for high frequency amplification to a heat sink. The coupling dielectric substrate should have the same circuit constants at the high-frequency circuit as the main dielectric substrate.

Abstract: Described is a flexible adhesive formulation for bonding a semiconductor device to a flexible substrate and a flexible card containing a semiconductor device which can be processed in a computer.

Abstract: A substrate includes a non-conductive support layer and a plurality "n" of conductive leads disposed on the support layer. The leads are arranged in a generally radial pattern about a central point on the support layer, each of the leads having a width "w" and spaced a distance "d" from one another at their innermost ends, thereby forming a generally square opening of side dimension "s". The substrate accommodates semiconductor dies ranging in size from smaller than the opening, to approximately equal to that of the opening, to substantially larger than the opening, such as four times the size (linear dimension) of the opening. The die is bonded to the substrate. Other elements of a semiconductor device assembly are added to the resulting structure. Method and apparatus are disclosed.

Abstract: An optical pickup apparatus in which light from a light source is led to an information medium and reflected light from the information medium is led to a hologram to be incident as a +1st order diffraction beam on a photodetector to obtain information signals. The hologram has a stair-like cross-sectional configuration, and a ratio of the width of a step of the stair-like cross-sectional configuration relative to a grating pitch of the hologram is arranged to vary in accordance with a position within a surface of the hologram.

Abstract: A semiconductor chip package wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that has a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Abstract: An integrated circuit having a semiconductor layer having formed therein a electronic circuit. An electrical device, electrically connected to the electronic circuit, has a corrugated platform supported over, displaced from, and integrally formed with, the substrate. In a preferred embodiment the electrical device is a bolometer and the electronic circuit is a read out circuit for the device. The platform includes a surface member and a leg, a proximate end of the leg being disposed on the substrate and the distal end being elevated from the substrate and terminating at the surface member. Preferably the leg and the surface member are corrugated. The supporting surface has a corrugation parallel with the leg. The surface member is supported, as a corrugated air-bridge, over the surface of the substrate by corrugated legs. The temperature sensitive resistive material is formed over the corrugated surface member.

Abstract: A resin sealed semiconductor device has a plurality of current-detecting resistors mounted and electrically connected in parallel on leads of a lead frame for detecting the current flowing in a semiconductor element mounted on the lead frame. Mounting n current-detecting resistors in parallel reduces the increase in resistance due to mounting to 1/nth the conventional value. Accordingly, changes in resistance values during mounting are minimized for accurate current measurement.

Abstract: In a semiconductor device of gate self-alignment structure, at least two lamination layer portions each composed of a gate electrode, an insulating film and a conductive film are formed on a semiconductor substrate with a contact hole sandwiched therebetween. A wire is formed on the respective lamination layer portions. Further, a total thickness of the conductive film and the wire is determined to be large enough to prevent impurities implanted into the wire from being doped into the gate electrode. In formation of the gate self-alignment structure, an insulating side wall is formed on the side wall of the contact hole, to insulate the gate electrode from the wire or vice versa.

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Abstract: A semiconductor element mounting die pad is supported by tie bars. Plural slits and dimples are disposed on a flat surface. The slits are penetrating from the face to the back side of the semiconductor element mounting die pad. Slits are formed, for example, by a punching or chemical etching method. These forming methods are the same as the method of forming the lead frame. Accordingly, if slits are disposed simultaneously when forming the lead frame, the process is not complicated. It is also possible to form these slits using the prior art. Slits of the same shape are formed at an interval of the width of dimples. The rear side is pushed out by press means to form dimples with the boundary of the slits. Thus, slits are formed in one body at both ends of the dimples. By thus composing, the thin type surface mount semiconductor device has a sufficient mechanical strength, and is capable of controlling the stress in a narrow region, so that a semiconductor device of high reliability is realized.

Abstract: A TAB Grid Array (TGA) pack package for an integrated circuit. A TGA package provides an efficient structure and method to connect a semiconductor die encapsulated in the TGA package to an external printed circuit board (PCB). The TGA package uses a tape automated bonding (TAB) technique to provide a generally flexible dielectric film bearing a pattern of conductive traces radially emanating from a die aperture to connect to an area array of pads arranged on the tape perimeter. The pads of area array of pads are connected to the TAB traces using conventional TAB inner lead bonding techniques, or alternatively, wire bonding methods, with both the semiconductor die and the TAB traces facing down towards the PCB. In one embodiment, the back of a semiconductor die and the TAB tape are attached to a stiffener via suitable bonding agents. The stiffener provides the mechanical rigidity to the package and efficiently removes the dissipated power.

Abstract: In a semiconductor memory device, and in particular in a NAND-type ROM memory cell, the transistors of a memory cell region and a peripheral circuit portion are manufactured to include a first and second impurity regions. The second impurity region has a higher impurity density impurity than the first impurity region. A third impurity region is added which has a higher impurity density and shallower depth than the impurity density of the first impurity region. Accordingly, the conventional transistor structure of the peripheral circuit portion is maintained while the transistors of the memory cell are optimized to have ideal electrical characteristics, including an increased current driving capability.

Abstract: A semiconductor memory device in which a protection layer is disposed between a silicon storage electrode and a tantalum pentoxide dielectric layer. A conductive material having a larger free energy of oxide formation than that of the tantalum pentoxide is used for forming the protection layer. Therefore, no native oxide film is formed at the interface between the storage electrode and the dielectric layer. As a result, the dielectric constant of the dielectric layer does not decrease even when the dielectric layer is a thin film.

Abstract: A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another.

Abstract: An LED spacer assembly includes a housing having at least one first passageway which permits the insertion of an LED. The LED has leads which extend therefrom and pass through the first passageway of the housing. The housing also includes at least one second passageway which intersects the first passageway and includes an extended portion. The second passageway permits the insertion of a tool or forming die element for the purpose of holding the leads and forming a bent portion in the leads which extend into the extended portion of the second passageway. The positioning of the bent portion of the leads into the extended portion of the second passageway permits the stable retention of the LED on the housing. Additionally, by holding the leads during the bending of the same, stresses on the LED are minimized during the assembly process.