Abstract: A semiconductor device of band-to-band tunneling type including a silicon substrate, a first gate electrode formed by a highly doped surface region of the silicon substrate, a first silicon oxide film formed on a surface of the surface region, a silicon thin film formed on the first silicon oxide film, a second silicon oxide film formed on a surface of the thin silicon film, and a second gate electrode formed by a metal film applied on a surface of the second silicon oxide film. In the thin silicon film, there are formed P and N type regions side by side to constitute a PN junction. When a gate bias voltage is applied across the first and second gate electrodes, a band bend having a large height and inclination in a direction perpendicular to the thin silicon film is produced in the depletion region in the vicinity of the PN junction.

Abstract: A semiconductor memory device with a storage capacitor is provided which accomplishes a large storage capacity together with a high component density, and facilitates the production. A switching transistor is formed locally in a semiconductor substrate. Formed over the transistor is an upper-level wire disposed over which is a storage capacitor. A storage capacitor contact passes through the upper-level wire. While ensuring a good capacity for the storage capacitor contact, the allowance of focus, too, can advantageously be obtained in simultaneously transferring a pattern of the upper-level wire onto the memory cell region as well as onto the peripheral circuit region. Particularly, by having the storage capacitor contact pass through a bit line, a drain and a source can symmetrically be arranged with a word line, like a memory cell with a bit-line-over-storage-capacitor organization cell. This eliminates an excess portion resulting in increasing the density.

Abstract: A compact optical system 10 for use with a single light valve full color system. The compact optical system 10 includes a prepolarizing beamsplitter 12 which extracts a beam of horizontally polarized light form an unpolarized/analyzer 14. The polarizer/analyzer 14 transmits the beam to a first dichroic separator 16 which transmits the red and green components and reflects the blue component toward a first fold mirror 18. The mirror 18 reflects the beam of blue light to a first fold prism 22 and to a first region 21 of a liquid crystal layer 19 of a light valve 23. A second dichroic separator 20 reflects the red beam component toward a second fold prism 24 and transmits the green component to a third fold prism 26. The prisms 24 and 26 direct the red and green beams toward second and third regions 25 and 27, respectively.

Abstract: A superconducting tunnel junction is disclosed herein. The superconducting tunnel junction is characterized in that a pair of oxide superconducting layers thereof and a tunnel barrier layer located between the oxide superconducting layers have the same or almost the same crystal structure and the same or almost the same lattice constant in a direction of a, b, or c axis. The layers have good crystallization.

Abstract: In a semiconductor P/N junction device, a porous emitter is provided which has high saturation current to limit injected charge when the device is conducting. The porous emitter includes a lightly doped region abutting a contact on the surface of the device to regulate minority carrier injection under forward bias and shield the contact from stand-off field when the device is not conducting. One or more heavily doped regions are provided in the first region to provide low contact resistance for the flow of majority carriers into the emitter.

Abstract: Optoelectronic semiconductor devices which have a groove-shaped waveguide in an oxide layer provided on a silicon substrate are compact, easy to manufacture, and--when the waveguide comprises a non-linear optical material--applicable inter alia for frequency doubling of laser radiation. In known devices, scattering losses occur in the waveguide owing to the roughness of the groove which arises during etching of the groove. Here, the groove and a portion of the oxide layer are formed by local, preferably thermal, oxidation of the silicon substrate. The groove formed at the area of the oxidation mask has a smoother surface and as a result the waveguide has lower losses. When the device includes a GaAs/AlGaAs diode laser, it forms an efficient, compact, inexpensive and blue-emitting laser source which is suitable for use in an optical disc system. Preferably, the diode laser is situated in a deeper and wider further groove in the oxide layer.

Abstract: The invention comprises a semiconductor package which allows pinouts and bond options to be customized after the encasement of a die in plastic, ceramic, or other suitable materials. A first embodiment of the invention has a first assembly comprising an encapsulated die having bond pads connected to bond wires which terminate in exterior pad portions on the exterior of the encapsulant. Conductive paths which are part of a second assembly electrically connect with the exterior pad portions of the first assembly and pass signals to device pinouts, which can be leads or other connecting means, to an electronic device into which the module is installed. By selectively connecting the exterior pad portions of the first assembly to the connection points of the conductive paths of the second assembly, the device pinouts and bond options can be selected. To manufacture a device having different pinouts or bond options, a bottom section having a different design is used.

Abstract: A packaged device with a lead frame, a lead frame and an article of manufacture comprising a base metal, a layer of nickel on the base metal, and a protective composite of metal layers on the nickel. The composite includes, in succession from the nickel layer, a layer of palladium or soft gold strike, a layer of palladium-nickel alloy, a layer of palladium and a layer of gold. The palladium or soft gold strike layer acts primarily as a bonding (an adhesive) layer between the Ni and Pd-Ni alloy layers and as a layer that enhances reduction in porosity of subsequent layers, Pd-Ni alloy layer acts as a trap for base metal ions, Pd layer acts as a trap for Ni ions from the Pd-Ni alloy layer, and the outer gold layer synergistically enhances the quality to the Pd layer. The various layers are in thickness sufficient to effectively accomplish each of their designated roles, depending on the processing and use conditions.

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Abstract: An HTSC material epitaxially deposited on a YSZ buffer layer on a surface of a monocrystalline silicon substrate has a zero resistance transition temperature of at least 85.degree. K., a transition width (10-90%) of no more than 1.0.degree. K., a resistivity at 300.degree. K. of no more than 300 micro-ohms-centimeter and a resistivity ratio (at 300.degree. K./100.degree. K.) of 3.0.+-. 0.2. The surface of the silicon substrate is cleaned using a spin-etch process to produce an atomically clean surface terminated with an atomic layer of an element such as hydrogen with does not react with silicon. The substrate can be moved to a deposition chamber without contamination. The hydrogen is evaporated in the chamber, and then YSZ is epitaxially deposited preferably by laser ablation. Thereafter, the HTSC material, such as YBCO, is epitaxially deposited preferably by laser ablation. The structure is then cooled in an atmosphere of oxygen.

Abstract: An integrated circuit including a first device having respective input and output electrodes at opposed first and second faces of a semiconductor block in which the device is formed, and a second device, formed in the semiconductor block, having its respective input and output electrodes at the first and second faces of the semiconductor block, the electrodes at the first face of the semiconductor block intermingling with each other. In one form of the integrated circuit, the electrode of the first device at the first face of the semiconductor block includes a plurality of discrete contact areas distributed over substantially all of the first face, and the electrode of the second device at the first face includes a contact area which lies between the discrete contact areas.

Abstract: It is the object of this invention to improve the breakdown voltage between the source and the drain of a MOS transistor having radiation resistance. A high concentration impurity having the same polarity as that of the source-drain region is formed below a gate oxide film at both ends in the channel width direction of the source-drain region of the MOS transistor. An impurity region having the same polarity as that of the source-drain region and an impurity concentration lower than that of the source-drain region is formed between the high concentration impurity region and the source-drain region.

Abstract: A memory for a dynamic random access memory includes an isolation trench formed between a pair of cells. Pass gate transistors are formed on either side of the isolation trench, with source/drain regions for contacting to a bit line formed on the opposite side of a gate electrode from the isolation trench. A source/drain region for each transistor is formed between the gate electrode and the isolation trench, and is used for a charge storage capacitor connection. For each transistor, a conductive plug is formed in contact with the capacitor source/drain region and extending vertically above this region and the gate electrode. This conductive plug forms the charge storage node of the capacitor, and is covered by a dielectric layer and a common capacitor reference plate.

Abstract: In a thick multilayered wiring board, a coaxial signal wiring pattern is surrounded by upper and lower horizontal grounded conductive layers and vertical grounded conductive layers and the vertical conductive layers of conductive layers which surround the coaxial signal wiring pattern are formed in a photosensitive dielectric layer by a photolithography, whereby matching of characteristic impedance of the pattern is improved and thus crosstalk is reduced.

Abstract: Body to drain junction breakdown, due to avalanching in DMOST devices, can be controlled. The invention lowers the electric field gradients in the vicinity of the PN junction. The structure employed to enhance breakdown behavior is specifically applied to a vertical DMOST. The N type doping profile in the vicinity of the body to drain junction is tailored by constructing a P-nu-N-N.sup.+ type diode structure where nu is a low N type impurity concentration region. The N type region is of higher impurity concentration and is more extensive. With the nu region having one-half of the impurity concentration of the N region and an extent of about two microns, the avalanche breakdown voltage is about 27% higher than the conventional PN junction diode. By making the nu region impurity concentration one-fourth that of the N region, the breakdown voltage is 40% higher.

Abstract: An optoelectronic integrated circuit includes a light responsive element for converting an optical signal into an electrical signal and an electronic circuit for processing the electrical signal. The light responsive element is disposed on a first surface of a substrate and includes p side electrodes and n side electrodes alternatingly arranged parallel to each other. The electronic circuit is disposed on a second surface of the substrate. The light responsive element is electrically connected to the electronic circuit by a via hole penetrating the substrate. In this structure, light incident on the first surface is almost completely absorbed by the substrate and hardly reaches the electronic circuit on the second surface. Therefore, variations in operation of the electronic circuit, such as an increase in drain current, are reduced.

Abstract: A semiconductor integrated circuit device wherein terminals other than clock signal terminals in circuit blocks are connected via a first wiring layer to a clock signal source and only the clock signal terminals in the blocks are connected via a second wiring layer to the source. The second wiring layer is formed above the first wiring layer and is connected to the clock signal terminals. Since the second wiring layer is dedicated to the clock signal, clock signal wiring can be laid out as desired when a layout is designed by a hierarchical design technique. There is no chance that propagation characteristics of the clock signals to the blocks deviates, and a cell area can be reduced. Preferably, a third wiring layer connected to the second wiring layer is furthermore provided for dedication to the clock signal.

Abstract: A lateral pnp transistor for use in programmable logic arrays. The lateral pnp has a layer of oxide disposed between a polysilicon layer and the base along the base width. The oxide layer prevents diffusion of the N+ dopant contained in the polysilicon layer into the N- base region. The base region thus remains N- and the resulting transistor has improved breakdown voltage characteristics while retaining the speed advantages of polysilicon contact layers. The lateral pnp transistor is manufactured by a method which requires minimal deviation from other methods used to manufacture lateral pnp transistors.

Abstract: A semiconductor lead frame wherein the chip pad and leads are contained within a separate inner island attached to an outer frame through a plurality of independent connectors spread around the perimeter of the island. Each connector consists of a curved filament capable of compression or expansion, thereby allowing the inner island to undergo some structural deformation without transmitting it to the outer frame. As a result, alignment holes contained in the frame are not affected by mechanical stresses suffered during the molding stage of the packaging operation. Separate alignment apertures may be added to the island portion of the lead frame as additional reference markers for post-molding alignment.

Abstract: A part of a polycrystalline silicon film forming a grounding line in a memory cell of a high-resistance load type SRAM, located immediately below a contact hole for connection between a polysilicon power supply line part and an aluminum power supply line part, is separated and isolated from the remaining part of the polycrystalline silicon film to form an island-like part. The contact hole extends through an interlayer insulating film below the aluminum power supply line part, the polysilicon power supply line part and another interlayer insulating film above the island part, and reaches the island part, whereby the aluminum power supply line part contacts even the island part through the contact hole. The island part also contacts the polysilicon power supply line part through another contact hole, whereby low-resistance contact can be obtained between the aluminum and polysilicon power supply line parts through the island part.