Abstract: A ferroelectrics device includes a semiconductor substrate having a diamond structure or zinc blend structure, and a ferroelectric compound film formed on the semiconductor substrate by selective epitaxial growth. The ferroelectric compound film is made of a mixed crystal of at least three components in groups II and VI and has the same structure as the semiconductor substrate.

Abstract: A semiconductor device is provided which includes a conductive layer, an insulating film formed on the surface of the conductive layer, and a conductive metal interconnection layer formed on the insulating film and electrically connected to the conductive layer through a contact hole formed in a predetermined position of the insulating film. The conductive metal interconnection and the surface of the conductive layer are directly joined together and a silicon layer including a single crystal or polycrystalline silicon having a grain size of at least about 10 .mu.m is interposed between the conductive metal interconnection layer and the insulating film. The conductive metal interconnection layer becomes a single crystal or a polycrystal having a grain size of about 10 .mu.m or above under the influence of the crystalline properties of the underlying crystal of the silicon layer.

Abstract: A resin-molded multi-chip package semiconductor device includes a lead frame having a plurality of leads including crossing leads that extend over an obverse or a reverse side of one semiconductor element separated from electrical contact with the element by an interposed insulating material. The electrodes of one element and of another element are electrically connected in common to the crossing lead by bonding wires. The device may comprise a TAB tape having leads on an insulating tape, electrically connecting the electrodes of the neighboring elements together. The TAB tape may include crossing leads that cross another TAB lead.

Abstract: A thin film single crystal substrate useful in the production of a semiconductor, comprising a base substrate made of single crystal diamond and at least one thin film of a single crystal of a material selected from the group consisting of silicon carbide, silicon, boron nitride, gallium nitride, indium nitride, aluminum nitride, boron phosphide, cadmium selenide, germanium, gallium arsenide, gallium phosphide, indium phosphide, gallium antimonide, indium arsenide, indium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, cadmium telluride, mercury sulfide, zinc oxide, zinc sulfide, zinc selenide and zinc telluride, and optionally an intermediate layer between the base substrate and the thin film of single crystal, which optionally comprises an intermediate layer between the base substrate and the thin film of single crystal.

Abstract: A semiconductor memory cell (10) having a symmetrical layout is fabricated in first and second active regions (44, 46) of a semiconductor substrate (11). A first driver transistor (16) resides in the second active region (46), and a second driver transistor (20) resides in the first active region (44). The second driver transistor (20) has a gate electrode (55) overlying a portion of the first active region (44) and is electrically coupled to the second active region (46). A thin-film load transistor (18) resides over the first active region (44), the thin-film load transistor (18) has a thin-film channel layer (23) that overlies, and is aligned with, the gate electrode (55) of the second driver transistor (20). A second portion of the thin-film channel layer (23) extends away from the first active region (44) to form a Vcc node (36). A Vcc interconnect layer (82) overlies the thin-film load transistors and the driver transistors.

Abstract: A radiation detector (1) includes a multi-layered substrate (2,10) having a first major surface, which is a radiation receiving surface, and a second major surface disposed opposite to the first major surface. A first detector is formed adjacent to the first major surface, the first detector being responsive to a wavelength or wavelengths of electromagnetic radiation in the range of approximately 0.3 micrometers (near-UV) to approximately 1.2 micrometers (near-IR). A second detector is formed adjacent to the second major surface of the multi-layered substrate, the second detector being responsive to a wavelength or wavelengths of electromagnetic radiation in the range of approximately one micrometer to approximately twenty micrometers (SWIR to VLWIR). In a presently preferred embodiment the second detector is simultaneously responsive to IR radiation within two distinct spectral bands.

Abstract: A field effect transistor includes a buffer layer, an undoped channel layer, and a N-type electron supplying layer which are sequentially deposited on a semi-insulating semiconductor substrate. The undoped channel layer is formed of an In.sub.x Ga.sub.1-x As layer. The In composition ratio in the InGaAs layer varies gradually in the direction of the thickness and has a maximum value at the position spaced away from the interface of the N-type electron supplying layer of the InGaAs layer by 40 .ANG. or more but less than 110 .ANG..

Abstract: A first gate layer of a first conductor layer is formed on a gate oxide layer and selectively covered with a second gate layer of a second conductor layer. The first and second gate layers are used as a mask and a semiconductor substrate is thermally oxidized to thereby increase a thickness of a portion of the gate oxide layer except the gate layers and cover the second gate layer and the portion having the increased thickness of the gate oxide layer with a third conductor layer. Thereafter, a side wall of an insulating layer is formed on a side portion of the second gate layer and is used as a mask to form a third gate layer. The first, second and third gate layers and the side wall are used as a mask and impurity is introduced into the semiconductor substrate relatively heavily to thereby form a heavily doped impurity layer.

Abstract: Type-II semiconductor heterojunction light emitting devices formed on a substrate are described wherein a graded injection layer is used to accelerate electrons over the electron barrier formed by the junction. Further, wide band gap semiconductor LEDs and lasers are proposed formed of II-VI materials which emit light in the blue and green wavelengths. Particularly, a system composed of n-CdSe:Al/Mg.sub.x Cd.sub.1-x Se/Mg.sub.y Zn.sub.1-y Te/p-ZnTe are described where the value of y determines the wavelength of the emitted light in the green or blue region and x varies across the graded injection layer for raising the energy levels of excited electrons.

Abstract: According to this invention, there is provided a semiconductor device including a TAB tape having through hole for an element, a plurality of leads integrally formed on the TAB tape, a semiconductor element connected to one end of each of the leads through a bump formed in the through hole for the element, a plurality of lead frames each connected to the other end of a corresponding one of the leads, and a mold resin sealed to cover the most part of the TAB tape, the leads, the semiconductor element, and the lead frames, wherein connection portions between the leads and the lead frames are linearly formed at equal pitches perpendicularly to an outer periphery of the semiconductor element opposite to the connection portions. Each of portions near positions where the leads are respectively connected to the lead frames is formed in a gull-wing shape.

Abstract: A semiconductor device aluminum-containing metallization system that is particularly useful for integrated circuits (ICs) having P-type contact regions and also having a likelihood of extended exposure to elevated temperatures. Use of an aluminum/silicon diffusion barrier formed of an amorphous tungsten/silicon on such ICs is made commercially practical. A titanium or transition metal silicide layer is disposed beneath the amorphous tungsten/silicon layer, to consistently provide durable low resistance electrical contacts to P-type regions of the IC.

Abstract: A junction field effect transistor, specifically a static induction transistor. The N-type source regions are formed as two zones. First, relatively lightly doped first zones are formed by ion-implanting doping material relatively deeply into the semiconductor material. Then relatively heavily doped second zones are formed by ion-implanting doping material to a relatively shallow depth within the first zones to leave portions of the first zones interposed between the second zones and the remainder of the semiconductor material. The resulting devices exhibit reduced gate-drain junction capacitance at low drain bias voltages thereby improving device capacitance linearity.

Abstract: A voltage controlled thyristor includes an intrinsic layer of material between an anode and a cathode and a gate region between the intrinsic layer and the cathode comprising a lightly doped P type layer with more heavily doped P type regions extending through the lightly doped layer into the intrinsic layer. The more heavily doped P type regions are interspersed among shallower N doped regions of the cathode. In a preferred embodiment, interdigitated ohmic contacts are formed on one surface to the N doped cathode regions and the P doped regions of the control gate. In a preferred embodiment, the anode and cathode emitters have a porous construction in which a lightly doped layer or region has a more heavily doped region or regions therein.

Abstract: A thin-film transistor comprises a gate electrode formed on an insulating substrate, a gate insulating film covering the gate electrode and the insulating substrate, an i-type semiconductor layer formed on the gate insulating film, and a source electrode and a drain electrode electrically connected to two ends of the i-type semiconductor layer, respectively. The gate electrode is made of aluminum alloy containing high-melting-point metal such as Ti and Ta and oxygen or nitrogen or both.

Abstract: The improved photodiode array has a structure that has pn-junctions arranged in a row on a semiconductor substrate 1 having an oxide film 2. The photodiode array has such a surface pattern that n-type impurity diffused layers 3 and p-type impurity diffused layers 4 are arranged in a generally concentric manner or with layers of one diffusion type alternating with layers of the other diffusion type. The improved process of fabrication comprises joining the oxide film 2 on the semiconductor substrate 1 to an n-type semiconductor layer 3 and then diffusing a p-type impurity within the n-type semiconductor layer 3 to form pn-junctions, thereby yielding a photodiode array. Thereby, it is provided a photodiode array that has such a simple structure that not only is he yield of device fabrication improved but also the cost of the final product is reduced.

Abstract: This invention relates generally to structure and method for preventing metal diffusion between a noble metal layer and an adjoining non-noble metal layer, and more specifically to new structures and methods for providing a superbarrier structure between copper and an adjoining noble metal layer. This is achieved by sequentially deposited a layer of non-noble metal, a layer of titanium, a layer of molybdenum, and a layer of noble or relatively less noble metal as the interconnecting metallurgy. This invention also relates to an improved multilayer metallurgical pad or metallurgical structure for mating at least a portion of a pin or a connector or a wire to a substrate.

Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) and the method of fabrication therefor. First a layered wafer is prepared on a semi-insulating GaAs substrate. The bottom wafer layer is n.sup.+ GaAs, followed by n.sub.- AlGaAs, a thin layer of n AlGaAs (which form the DHBT's collector) and a base layer of p.sup.+ GaAS. A layered plug fills a trench etched in the base layer. The bottom two plug layers are AlGaAs and the top plug layer is GaAs. Next, an emitter is ion-implanted into the plug core and an extrinsic base region is ion-implanted. Finally, base, emitter and collector contacts are formed.

Abstract: A semiconductor device comprising a capacitor which comprises a lower electrode, a dielectric insulating film of a metal oxide, and a upper electrode. The lower electrode is made of at least yttrium (Y) or hafnium (Hf).

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.