Patents Examined by Andrew J. James
  • Patent number: 5384480
    Abstract: A clear-mold solid-state imaging device using a charge coupled device, in which a solid-state imaging device is molded with a transparent resin. The solid-state imaging device includes a surface having a light receiving section; a light shielding film provided over the surface; a transparent passivation film for protecting the light shielding film; and a moving ion blocking layer provided between the transparent passivation film and the transparent resin.
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: January 24, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shun-ichi Naka, Takayoshi Ishida
  • Patent number: 5384487
    Abstract: A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: January 24, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5384488
    Abstract: A semiconductor chip (12) includes a plurality of bond pads (16). A plurality of bond shelves (28) are located along opposed end edges (20, 22) of the chip (12). The bond pads (16) are oriented in selected areas remote from the bond shelves (28). A via (42) is formed through an insulating layer (38) to the surface of the bond pad (18) to provide electrical connection thereto. A metallization layer (44) is formed over the an insulating layer (38), filling the via (42). The metallization layer (44) is patterned and etched to form a patten of trace lines (18) spatially separated to connect each bond pad (16) to bond shelves (28).
    Type: Grant
    Filed: October 3, 1993
    Date of Patent: January 24, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Shahin Golshan, Craig A. St. Martin, Craig W. Rhodine
  • Patent number: 5384482
    Abstract: An input protective circuit provided between a semiconductor integrated circuit and an input bonding pad formed on a semiconductor substrate includes an N or P type electric field intensity relaxing region for setting a clamp level of the input protective circuit. The electric field intensity relaxing region is formed between an N.sup.+ -type semiconductor region connected to an input wiring layer and a P.sup.+ -type semiconductor region connected to a reference potential wiring layer.
    Type: Grant
    Filed: May 18, 1993
    Date of Patent: January 24, 1995
    Assignee: NEC Corporation
    Inventor: Yasutaka Nakashiba
  • Patent number: 5382812
    Abstract: A light emitting semiconductor heterojunction includes a first layer of n-type semiconducting material comprising a Group II-VI material, and a second layer of p-type semiconducting diamond on the first layer. Preferably the Group II-VI material includes a Group II material selected from the group consisting of zinc and cadmium, and the Group VI material is selected from the group consisting of sulfur and selenium. The light emitting heterojunction will produce light having a wavelength in the range of about 440-550 nanometers, depending on the composition and the temperature of operation. One embodiment of the device is a surface emitting device and includes a contact layer on the diamond layer having a predetermined shape, such as a ring, overlying only a portion of the diamond layer for permitting surface emission of light from diamond layer.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: January 17, 1995
    Assignee: Kobe Development Corporation
    Inventor: David L. Dreifus
  • Patent number: 5382823
    Abstract: A semiconductor device includes a cavity portion formed in a supporting portion made of a semiconductor material so as to be surrounded by the supporting portion, and a silicon oxynitride film supported on one surface of the supporting portion so as to cover the cavity portion on the side of the one surface or a silicon oxynitride film supported on one surface of the supporting portion and so arranged as to form a bridged structure over the cavity portion. The composition of the silicon oxynitride film is selected in accordance with the material of the supporting portion.
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: January 17, 1995
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Kiyoshi Komatsu, Takeshi Kudo
  • Patent number: 5382813
    Abstract: A light emission diode comprises a semiconductor substrate and a pn junction structure including an n-type ZnS compound semiconductor layer and a p-type ZnS compound semiconductor layer, Al being present in at least one of the semiconductor layers. By this, the diode is able to emit blue light at a high luminous intensity.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: January 17, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshio Morita
  • Patent number: 5382829
    Abstract: A semiconductor device including an insulating film substrate having a surface, a high frequency semiconductor chip disposed on the surface, and circuit elements disposed on the surface and connected to the semiconductor chip wherein the insulating film substrate is bent into a U-shape, laminated, and encapsulated with a resin. The package of the device is miniaturized.
    Type: Grant
    Filed: March 17, 1993
    Date of Patent: January 17, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akira Inoue
  • Patent number: 5381042
    Abstract: A low cost electronic device package having greatly improved heat dissipation capability. The package includes a heat slug, preferably formed from oxygen-free high-conductivity copper, that has a surface exposed outside the package. A simplified and inexpensive manufacturing method is described using a "drop in" technique. Using this technique, the size and shape of the heat slug is dependent only on the size and shape of the mold cavity; the package may have any number of leads and any size die. The heat slug is preferably formed with fins around its circumference so that the slug is self-aligning when it is dropped into the mold cavity. Preferably, slots are formed through the heat slug to provide improved encapsulant flow during the encapsulation process and interlocking between slug and encapsulant in the finished package.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: January 10, 1995
    Assignee: Amkor Electronics, Inc.
    Inventors: Steve P. Lerner, David S. Razu
  • Patent number: 5381030
    Abstract: The semiconductor memory device according to the present invention includes a memory cell array region in which memory cells are arranged in array form, a first and a second row decoders arranged respectively on both sides of the memory cell array region, and a plurality of metallic wirings which are arranged within the memory cell array region in parallel to row direction, the respective one ends of the wirings are alternately connected to either of the first row decoder or the second row decoder, and the width of the metallic wirings that extend from the first or the second decoder to predetermined locations within the memory cell array region is greater than the width of the metallic wirings that extend beyond the predetermined locations within the memory cell array region.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: January 10, 1995
    Assignee: NEC Corporation
    Inventor: Naoki Kasai
  • Patent number: 5381038
    Abstract: An electrode construction intended to facilitate soldering with a semiconductor disc element having a pair of electrode plates soldered to a semiconductor chip with the semiconductor chip held between the electrode plates. A stepped protrusion is disposed on the central part of each electrode plate such that the stepped protrusion is directed into a solder joint of the semiconductor chip. While the stepped protrusion is held in the solder joint of the semiconductor chip, the electrode plate floats above a passivation on the semiconductor chip side before being soldered to the semiconductor chip. The electrode plates have orientation slits and orientation flats as references for positioning purposes. The electrode plates, semiconductor chip, and stepped protrusions are protected by a uniform layer of shrinkage tube.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: January 10, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yoshitomo Ogimura, Kenzi Motai
  • Patent number: 5381036
    Abstract: A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.
    Type: Grant
    Filed: August 16, 1993
    Date of Patent: January 10, 1995
    Assignee: Motorola, Inc.
    Inventors: Charles G. Bigler, James J. Casto, Michael B. McShane, David D. Afshar
  • Patent number: 5381033
    Abstract: A dielectrics dividing wafer is disclosed in which embedded dielectric films are provided in the interior of the wafer in a predetermined pattern extending laterally parallel to a face surface of the wafer, and partition dielectric films, in the form of vertical walls extending from the face surface and the rear surface of the wafer, to the embedded dielectric films, are provided to define semiconductor areas extending continuously from the face surface of the wafer to the rear surface of the wafer. The semiconductor areas can be used for vertical circuit elements. The partition dielectric films in conjunction with the embedded dielectric films and the face surface of the wafer also define additional planar semiconductor areas that can be used for planar structure circuit elements.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: January 10, 1995
    Assignee: Fuji Electric Company, Ltd.
    Inventor: Kazuo Matsuzaki
  • Patent number: 5381037
    Abstract: A high performance hermetic integrated circuit package assembly for housing an integrated circuit die wherein the package assembly affords substantially reduced ground bounce within the integrated circuit. The package assembly includes a lead frame of electrically conductive material having a first predetermined pattern of outer leads and a second predetermined pattern of, integrally connected, inner leads for providing interconnection to the die through a plurality of contact pads thereon, a series of electrically conductive wires connecting selected ones of the contact pads to selected ones of the inner leads, a base for mounting the die and includes a first layer of glass for supporting the lead frame and, a cap with a second layer of glass for reacting with the first layer of glass to provide a hermetic enclosure for the die.
    Type: Grant
    Filed: June 3, 1993
    Date of Patent: January 10, 1995
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jerry Olivarez
  • Patent number: 5381047
    Abstract: A semiconductor integrated circuit of the laminated type having a large circuit capacity includes an upper silicon tip and a lower silicon tip as essential components and a layer of electrical insulative material is interposed between the upper silicon tip and the lower silicon tip both of which are electrically connected to each other via a number of lead wires extending therebetween. An assembly of the upper silicon tip, the electrical insulative material layer and the lower silicon tip is fixedly mounted on a base board, and the foregoing assembly is then covered with a cap.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: January 10, 1995
    Inventor: Kazumasa Kanno
  • Patent number: 5378925
    Abstract: In a semiconductor integrated circuit device such as a memory chip, the number of wirings is increasing as the memory capacity and the like increase. In improving the reliability and obtaining high access speed of a common bus in which these wirings are arranged, wirings in a second layer and via holes at jumpers used for interference portions of signal wirings and power supply wirings in a congested region of a common bus have become an issue. Accordingly, in the present invention, it is made possible to form wirings in the second layer having wide width and a plurality of via holes per one connecting point, thus realizing a semiconductor integrated circuit which has high reliability and high access speed by arranging a mother power supply wiring branched to the common bus line along the vicinity of processing circuits of signal wirings arranged in the common bus.
    Type: Grant
    Filed: May 18, 1992
    Date of Patent: January 3, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Sasaki
  • Patent number: 5376624
    Abstract: A Josephson break junction device suitable for highly sensitive electronic detecting systems. A superconductor film such as YBa.sub.2 Al.sub.3 O.sub.7 is deposited on a substrate such as a single-crystal MgO. The film is fractured across a narrow strip by at least one indentation in the substrate juxtaposed from the strip to form a break junction. A transducer is affixed to the substrate for applying a bending movement to the substrate to regulate the distance across the gap formed at the fracture to produce a Josephson turned junction effect. Alternatively, or in addition to the transducer, a bridge of a nobel metal is applied across the gap to produce a weak-link junction.
    Type: Grant
    Filed: October 10, 1991
    Date of Patent: December 27, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ignacio M. Perez, William R. Scott
  • Patent number: 5376823
    Abstract: A lateral bipolar transistor includes an insulating substrate, a single crystal semiconductor layer having a first conductivity, a mask layer which has a substantially vertical side surface and which is in contact with the single crystal semiconductor layer, and an insulating sidewall formed along the side surface of the mask layer. A base region is located under the insulating sidewall and formed in the single crystal semiconductor layer. The base region has a second conductivity opposite to the first conductivity and contains an impurity implanted by an ion implantation process. The single crystal semiconductor layer has an underlying portion on which the mask layer and the insulating sidewall are formed. An emitter region is formed in a first portion of the single crystal semiconductor layer other than the underlying portion. A collector region is formed in a second portion of the single crystal semiconductor layer other than the underlying portion.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: December 27, 1994
    Assignee: Fujitsu Limited
    Inventors: Manabu Kojima, Naoshi Higaki
  • Patent number: 5373188
    Abstract: A resin-molded multi-chip package semiconductor device includes a lead frame having a plurality of leads including crossing leads that extend over an obverse or a reverse side of one semiconductor element separated from electrical contact with the element by an interposed insulating material. The electrodes of one element and of another element are electrically connected in common to the crossing lead by bonding wires. The device may comprise a TAB tape having leads on an insulating tape, electrically connecting the electrodes of the neighboring elements together. The TAB tape may include crossing leads that cross another TAB lead.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: December 13, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazunari Michii, Koichi Nakagawa
  • Patent number: 5373187
    Abstract: A package body for an integrated circuit is provided with a substrate having a mounting portion for mounting the integrated circuit. A terminal member for high speed signal input-output is provided on a portion of the substrate except the mounting portion of the substrate. A high speed signal transmission line has one end portion to be connected to the integrated circuit and the other end portion connected to the terminal member and is formed at a portion of the substrate except the mounting portion of the substrate. A plating tie-bar is formed at the substrate so as to extend from an outer periphery edge of the substrate inwardly for electrolytically plating the one end portion of the high speed signal transmission line and the terminal member.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: December 13, 1994
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Katuaki Sugino, Masahito Morita