Abstract: A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET).

Abstract: In an SIP type module of the type wherein memory ICs are mounted to both surfaces of a substrate, the present invention provides a face package type memory module wherein packaging is made in an inclined direction in place of vertical packaging of the prior art technique and only the memory ICs mounted to the upper surface side of the substrate are deviated to the positions closer to the end portion of the substrate in order to drastically reduce the packaging height.

Abstract: A semiconductor assembly comprises first and second containers which contain respective semiconductor chips and are stacked one over another. First and second external leads extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other. The first and the second containers may be provided at corresponding positions with a recess and a projection to be engaged each other for positional alignment. There may be provided first and second heat radiating plates extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other.

Abstract: A silicon carbide photodiode exhibiting high short-wavelength sensitivity, particularly in the ultraviolet spectrum, and very low reverse leakage current includes a p type conductivity 6H crystalline substrate. A first p- silicon carbide crystalline layer is epitaxially grown on the body. A second n+ silicon carbide crystalline layer is epitaxially grown on the first layer and forms a p-/n+ junction with the first layer. A metallic upper contact layer is formed on a predetermined surface region of the second layer oppositely situated from the junction. The second layer is of a uniform minimum thickness, generally less than 1000 Angstroms, with a greater thickness, typically 3000-4000 Angstroms, beneath the predetermined surface region. The thicker portion of the second layer occupies less than 10% and generally less than 1% of the total second layer surface area.

Abstract: A transition crystal structure is disclosed for providing a good lattice and thermal match between a layer of single crystal silicon carbide and a layer of single crystal gallium nitride. The transition structure comprises a buffer formed of a first layer of gallium nitride and aluminum nitride, and a second layer of gallium nitride and aluminum nitride adjacent to the first layer. The mole percentage of aluminum nitride in the second layer is substantially different from the mole percentage of aluminum nitride in the first layer. A layer of single crystal gallium nitride is formed upon the second layer of gallium nitride. In preferred embodiments, the buffer further comprises an epitaxial layer of aluminum nitride upon a silicon carbide substrate.

Abstract: A semiconductor device and a method of making the same capable of simplifying the process of making and reducing the cost of making. In the method a first layer is formed which has a plurality of conductors at its edge portion. Thereafter, a second layer is formed on the first layer which is to be selectively etched to form a pattern. During the etching, current is detected from the conductors and the etching is stopped dependent on the current detected from the conductors. The semiconductor device includes a transparent electrode on a substrate the transparent electrode having protrusions which have a top surface. A first insulation layer exists between the protrusions. There is a color emitting layer on the top surfaces of the protrusions and the insulation layer.

Abstract: A semiconductor integrated circuit device with high power noise immunity and high substrate surge immunity. An LOC lead frame to be connected to a power wiring for supplying a source voltage and a ground potential to input circuits of a semiconductor chip is isolated from another LOC lead frame for supplying the source voltage and the ground potential to other circuits. The source voltage and the ground potential for the circuit are supplied by way of external terminals formed by the respective lead frames. Further, the isolated LOC lead frames are connected to each other through a resistive impedance component formed on the semiconductor chip.

Abstract: A film of elastomeric material is used to laminate the tape with LGA outer lead bumps to the stiffner plate of the semiconductor package. The elastomeric material has the necessary physical and electrical characteristics to provide the required firmness to maintain good electrical contact between the outer lead bumps and the corresponding contacting pads on a socket, ceramic substrate or PWB, and at the same time, to provide the required resilience to accommodate differences in heights between the outer lead bumps. The stiffner plate is fabricated with a cavity at its center for accommodating the VLSI die, and slots along the outer edges of its underside for storing the excess elastomeric material squeezed out when laminating the tape to the stiffner plate, thereby preventing the excess squeezed out elastomeric material from building up at the outer edges of the semiconductor package to a height in excess of the outer lead bumps.

Abstract: A semiconductor device that has a feature in the spatial relationship between the wiring in a multi-level wiring and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wiring there exist intermediate insulating films that have a pattern which is the same as the pattern of the wiring. Because of this arrangement, the intermediate insulating film does not exist between the wiring on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure.

Abstract: In the semiconductor device according to the present invention, bonding pads are arranged on the periphery of the semiconductor chip and power supply inner leads are disposed inwardly of signal inner leads. Since bonding wires for connecting the signal lead to signal pads corresponding thereto do not extend astride of the power supply inner lead, a package of a semiconductor device can be thereby thinned as much as possible.

Abstract: A lead frame includes a stage portion, at least one bar-like support portion, a plurality of lead portions; and a connection portion. A semiconductor chip having pads formed on an upper surface of the semiconductor chip is mounted on the stage portion. The bar-like support portion supports the stage portion. The plurality of lead portions are arranged to surround the stage portion and connected to the pads of the semiconductor chip mounted on the stage portion, and the stage portion is arranged at a level lower than that of an arrangement surface of the lead portions. The connection portion is formed on one side of the stage portion perpendicular to a longitudinal direction of the support portion, and the connection portion has a central portion which has an upper side portion projecting almost parallelly to a surface of the stage portion at a level higher than that of the surface of the stage portion and is connected to the support portion on the same plane.

Abstract: An IC carrier has an IC body and a flexible wiring sheet superimposed on and contacted with the IC body. The carrier is loaded in a socket so that the wiring sheet may contact the socket. The socket comprises an elastic backup member for elastically pressing the superimposed portion of the wiring sheet so as to contact with the IC body. An operating device deflects the elastic backup member between the pressing position and a press-releasing position.

Abstract: A metal-core-type multi-layer lead frame adapted to be used for a semiconductor device includes a metal core plate on which a semiconductor chip is to be mounted. A plurality of signal lines are formed on the metal core plate. A metal plane, such as a power supply plane or a ground plane, is laminated on the signal lines, through an insulating layer, so that an outer peripheral edge of said metal core plate is uncovered to expose the outer portion of the respective signal lines. A lead frame body has a plurality of leads which are electrically connected to the respective signal lines at the outer peripheral edge of the metal core plate.

Abstract: An IC carrier comprising a carrier body carrying an IC body, which is either alone or received in a protective case, a wiring sheet with a lead pattern applied onto an upper surface thereof and on which the wiring sheet is superimposed in such a manner as to cover an outer upper surface of the IC body, a plurality of fine adjustment pushers for pressing the IC body or the protective case sidewardly at plurality of points in order to slightly move the IC body or the protective case along an inner upper surface of the wiring sheet to adjust the position of the IC body so as to correctly correspond to the wiring sheet, each of the fine adjustment pushers being formed of male screw pins which are threadedly engaged with the carrier body and reciprocally moved, the IC body or the protective case being pressed sidewardly by end faces of the male screws, respectively.

Abstract: A metal-to metal antifuse device is provided in a double layer metal interconnect structure. A lower electrode comprises a first multilayer metal layer interconnect disposed on an insulator. An inter-metal dielectric is disposed on the first metal layer interconnect having an antifuse via. An antifuse material layer is disposed in the antifuse via and having an upper electrode comprising a second multilayer metal layer interconnect.

Abstract: A light emitting diode is disclosed which comprises at least one heterojunction composed of silicon carbide (SIC) and semiconductor materials selected from the group consisting of gallium nitride (GAN), aluminum nitride (AlN), and aluminum gallium nitride (Ga.sub.x Al.sub.1-x N, 0<x<1).

Abstract: A semiconductor light emitting element in which light leakage from the vicinity of an active layer end thereof is significantly reduced, and an interval at which the element is disposed is sufficiently narrow, so that there can be realized an optimal distance-measuring accuracy when used for a light source of a camera's automatic focusing mechanism.

Abstract: Semiconductor device including a distributed-type monolithic integrated circuit on a substrate, operating in the high frequency and/or microwave range, this distributed circuit having a plurality of coupled stages each having at least a transistor with a first electrode being AC connected to ground. The first electrode is connected to ground by two branches, a first branch being connected directly to a first ground stub and a second branch being connected to a second ground stub through a resistor.

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract: An integrated circuit device has a substrate, a plurality of circuit elements or units arranged on the substrate and having terminals, a plurality of signal lines connected between the terminals of the circuit elements or units, or between the terminals and external connection terminals, and an alternating current ground line provided close to the signal lines to determine a transmission characteristic of the signal lines, the alternating current ground line including a high-potential direct current power source line and a low-potential direct current power source line, the high-potential direct current power source line and the low-potential direct current power source line being vertically separated by a dielectric layer.