Abstract: A p-type ZnO single crystal having a low resistance; and a method for producing the same providing a substrate (2) in a vacuum chamber (1), supplying to the substrate (2) atomic gases of Zn, O, and N (p-type dopant) and Ga (n-type dopant) in a manner wherein the feeds of N and Ga are controlled in such a manner that the ratio of N:Ga in a crystal is 2:1, and thereby growing a p-type ZnO single crystal containing N and Ga.

Abstract: A substrate with striped ridge patterns formed on the surface thereof is transported along a transport path. A relationship is determined between the direction of the striped ridge patterns on the substrate surface and the direction of jetting out fluid to the substrate surface. The fluid is jetted out and blown to the substrate surface along the direction satisfying the determined relationship to process the surface of the substrate. It is possible to reliably perform a surface process of each substrate irrespective of different directions of striped ridge patterns on substrate surfaces.

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate having formed thereover a minimum of one microelectronic layer, where the minimum of one microelectronic layer is at least partially transparent to an incident radiation beam. There is then chemical mechanical polish (CMP) planarized the minimum of one microelectronic layer, while employing a chemical mechanical polish (CMP) planarizing method, to form from the minimum of one microelectronic layer a minimum of one chemical mechanical polish (CMP) planarized microelectronic layer.

Abstract: The present invention provides a method for forming a dual-damascene structure and comprises following steps. First, a substrate is provided. Then, a first low-k dielectric layer and a second low-k dielectric layer are sequentially formed on the substrate. Next, a first via hole is formed in the first low-k dielectric layer by removing a portion of the second low-k dielectric layer and the first low-k dielectric layer. Thereafter a second via hole is formed in the second low-k dielectric layer by removing a portion of the second low-k dielectric layer, wherein the second via hole connects with the first via hole. Then, a conductive layer is formed to fill the first via hole and the second via hole. Next, the second low-k dielectric layer is removed. Last, a low-k dielectric layer is formed on the first low-k dielectric layer and exposes the conductive layer.

Abstract: A chemical mechanical polishing step is performed to expose a silicon/silicon dioxide interface on a surface situated on a semiconductor substrate. The semiconductor substrate is dipped in a solution of about 200 parts of deionized water, about 1 part of hydrofluoric acid, and at least 5 parts tetramethyl ammonium hydroxide. The exposed silicon/silicon dioxide interface is then contacted with an organic carboxylic acid surfactant having a critical micelle concentration greater than or equal to 1−7 m/l and having a pH from about 2.2 to about 7. Lastly, the exposed silicon/silicon dioxide interface is rinsed in deionized water or sulfuric acid to remove silicon dioxide particles from the exposed silicon/silicon dioxide interface, leaving a very clean, low particulate surface on both the silicon dioxide and silicon portions thereof, with little or no etching of the silicon portion.

Abstract: An improved and new process for fabricating self-aligned contacts (SAC) to source/drain areas of complimentary (CMOS) FET's has been developed using a non-conformal layer of silicon nitride, eliminating the need for a hard mask. This process allows for “zero” spacing from contact structure to polysilicon gate structure, for closely spaced design rule gates. Some key process features of this invention are as follows: no hard mask is needed and the gate process is exactly the same as “standard” logic process. The process differences are that between the S/D implant, salicidation and the normal contact process, there is inserted a non-conformal CVD silicon nitride deposition with a SAC pattern and etch process. The process is fully compatible with both state of-the-art salicide and polycide processes. The self-aligned contact process simplifies processing, while yielding improvements in electrical device performance and reliability.

Abstract: After an organic insulating film has been deposited over a semiconductor substrate, a silylated layer is formed selectively on the organic insulating film. Then, the organic insulating film is etched using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.

Abstract: An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 &mgr;m or more, while the finished surfaces have a surface roughness of only 15-50 Å (RMS).

Abstract: A method of producing a high-quality silicon single crystal of a large diameter and a long size in a good yield by controlling the positions where ring-like oxygen-induced stacking faults (R-OSF) occur in the crystal faces and minimizing grown-in defects such a dislocation clusters and infrared scattering bodies that are introduced in the pulling step. Wafers produced from the above-high-quality silicon single crystal contain little harmful defects that would deteriorate device characteristics and can be effectively adapted to larger scale integration and size reduction of the devices. Therefore, the method can be extensively utilized in the field of producing semiconductor silicon single crystals.

Abstract: Silicon carbide single crystal is produced by allowing a silicon raw material to continuously react with a carbon raw material to generate gas, which reaches a seed crystal substrate on which a silicon carbide single crystal grows. Preferably, the silicon raw material is continuously fed onto the carbon raw material placed in a reaction crucible, and the carbon raw material is maintained at a temperature such that carbon is allowed to react with silicon in a molten state or a gaseous state to generate the reaction gas.

Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.

Abstract: A plasma treatment apparatus according to the present invention includes a vacuum chamber, an upper electrode and a lower electrode disposed in the vacuum chamber, a high-frequency power supply for applying a high-frequency voltage, a space adjusting device for adjusting the spacing between the two electrodes, and a workpiece-transfer-device for transferring to and from a space between the two electrodes. The plasma treatment apparatus can decrease the spacing between the two electrodes and thereby increase the etching rate. Further, the workpiece can be easily transferred to and from the space between the two electrodes by opening the spacing.

Abstract: A method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate that can compensate for some misalignment between the filled vias and the lines. By alternately depositing liner-barrier layers and aluminum layers on the substrate, different etch chemistries can be used that can anisotropically etch an aluminum layer used to form the lines without etching voids in the aluminum-filled vias.

Abstract: A method for etching a surface of an integrated circuit. A layer of photoresist is applied to the surface of the integrated circuit. The layer of photoresist is exposed and developed, and the surface of the integrated circuit is etched with an etchant that contains chlorine. The surface of the integrated circuit is exposed to tetra methyl ammonium hydroxide to neutralize the chlorine, and rinsed with water.

Abstract: A method of batch fabrication of ultraminiature fiber optic pressure transducers including the steps of: providing a first substrate with a first sacrificial layer formed thereover; forming a plurality of light reflective diaphragm structures on the first sacrificial layer; forming a plurality of fiber stopper structures on the light reflective diaphragm structures; forming a plurality of fiber alignment cavity structures on the fiber stopper structures, the light reflective diaphragm structures, fiber stopper structures and fiber alignment cavity structures providing a plurality of fiber alignment assemblies; providing a second substrate with a second sacrificial layer formed thereover; forming a plurality of ferrule structures over the second sacrificial layer; inputting a plurality of fibers into the ferrule structures and sealing each of the ferrule structures to the fiber inserted therein, the ferrule structures and the fibers providing a plurality of fiber-ferrule assemblies; etching the second sacrific

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. An etch stop layer is formed over the surface of the substrate and the devices, and an inter level dielectric layer (ILD) is formed over the etch stop layer. An antireflection layer (ARC) is formed over the insulator layer, and a photoresist layer is formed over the insulator layer. The photoresist layer is photolithographically patterned to form first holes therethrough which overlie the interconnect areas. Using the patterned photoresist layer as a mask, second holes which underlie the first holes are etched using Reactive Ion Etching (RIE) through the antireflection layer to the insulator layer. Third holes are etched through the insulator layer down to the etch stop layer.

Abstract: A method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP process are obtained. The method includes the steps of: heat-treating a semiconductor device having an interlayer insulating film containing impurities; conducting a process for making an impurity-concentration distribution at an upper layer portion of the interlayer insulating film substantially uniform after the heat treatment; and polishing the interlayer insulating film by a CMP process after the process for making the impurity-concentration distribution substantially uniform.

Abstract: A notched gate configuration for high performance integrated circuits. The method of producing the notched gate configuration comprises forming a dielectric substrate and depositing a gate oxide layer, a conductive film layer, and a metal silicide layer over the gate oxide layer to form a conductive stack. A patterned silicon nitride mask layer is deposited over the conductive stack and over-etched to form a small notch in the metal silicide layer at each side of the patterned silicon nitride mask layer. This over-etching causes indentions to form in the conductive stack to result in decreased gate overlap between the gate and a source and drain which are later formed.

Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining.