Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

Abstract: Disclosed are a 3D display panel and the 3D display device. The 3D display panel includes a base plate, a plurality of pixel units, and first and second light emission units. Each of the pixel units includes at least one the sub-pixel, which includes primary and secondary pixel respectively corresponding to the first and second light emission units. Each of the two light emission units includes an anode, a hole transportation layer, an orientation layer, a light emissive layer, an electron transportation layer, and a cathode that are sequentially stacked. In the first and second light emission units, the orientation layers set the orientations of the light emissive layers to first and second orientation states, respectively, and first and second electrons and first and second holes respectively generated by the cathodes and anodes are recombined in the light emissive layers to respectively emit first and polarization light, which are orthogonal.

Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.

Abstract: A light-emitting device including a substrate, a first light-emitting diode disposed on the substrate, a molding member encapsulating the first light-emitting diode, and luminophores dispersed in the molding member and including a surface-modified luminophore, in which the surface-modified luminophore includes a fluorinated coating and a fluoride luminophore including a manganese activator. The fluoride luminophore is selected from the group consisting of K2SiF6, Na2SiF6, Rb2SiF6, K2GeF6, Na2GeF6, and Rb2GeF6.

Abstract: Application of a wavelength conversion element is substantially independent of the fabrication of a side-emitting light emitting device. In an example embodiment, the wavelength conversion element is situated around the periphery of a non-wavelength converting lightguide that is situated above the light emitting surface. One or more specular and/or diffusing reflectors are used to direct the light in the lightguide toward the wavelength conversion element at the periphery. In another embodiment, an interference filter may be used to provide predominantly side-emitted light at interfaces between the elements of the light emitting device.

Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.

Abstract: The invention relates to a process for producing a composite body (36) having at least one functional layer or for the further use for producing an electronic or optoelectronic component (40, 42, 44). The composite body (36) is in the form of a layer structure and comprises at least one substrate (34), which is in the form of a plate and has at least one planar substrate surface, and at least one substantially polycrystalline or at least one substantially single-crystal layer (38), which comprises at least one compound semiconductor, a ceramic material or a metallic hard material. The process is characterized by the following steps: heating at least part of the planar substrate surface to a temperature of at least 100° C. and at most 550° C.

Abstract: Provided is a method for creating a mask blank that includes a capping layer and a shifter layer. The capping layer is optically compatible and process compatible with the shifter layer. The method may include providing a cleaned and polished mask substrate to a deposition tool and depositing, within the deposition tool, a shifter layer over a cleaned and polished mask substrate. The shifter layer may include each material of a set of materials in a first proportion. The method may also include depositing an additional layer over the shifter layer, the additional layer providing a capping layer over the shifter layer. The capping layer includes the materials in a second proportion unequal to the first proportion. The capping layer includes molybdenum, silicon, and nitride in a proportion that aids in detection by a residual gas analyzer. Also provided is also a mask blank structure incorporating the compatible capping layer.

Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

Abstract: A transparent conductive oxide (TCO) material includes a metal-rich metal oxide having an average formula (M1, M2 . . . Mn)yOx, where M1, M2 and Mn are the same metal or different metals and a molar ratio of y:x is selected from a range of 0.1 to 20. A method of making a metal-rich metal oxide material includes co-depositing a metal and a stoichiometric metal oxide and annealing the deposited material above 100° C. In an embodiment, a thin-film solar cell, includes an electrode, a transparent conductive oxide (TCO) disposed on the electrode, a solar absorbing layer disposed on the TCO, and a metal-rich metal oxide disposed on the solar absorbing layer. A method of fabricating a thin-film solar cell is also disclosed.

Abstract: The present disclosure provides a light-emitting device. The light-emitting device comprises: a substrate; an intermediate layer on the substrate; a first window layer comprising a first semiconductor optical layer on the intermediate layer and a second semiconductor optical layer on the first semiconductor optical layer; and a light-emitting stack on the second semiconductor optical layer; wherein a difference between the lattice constant of the intermediate layer and the lattice constant of the first semiconductor optical layer is greater than 2.3 ?.

Abstract: Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns.

Abstract: A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin.

Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.

Abstract: A method for fabricating a Zinc Oxide (ZnO) conductive film on a semiconductor material, including depositing a doped ZnO seed layer on a diode, wherein the ZnO seed layer forms an electrical contact to the diode; and depositing a ZnO layer on the ZnO seed layer, wherein the ZnO seed layer and the ZnO layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising III-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the ZnO layers and the diode, and (2) a contact resistance, of a structure comprising the ZnO layers and the diode, is lower as compared to a contact resistance of a structure comprising the ZnO layer directly on the diode without the ZnO seed layer.

Abstract: The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10, and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10. The first resin molding 40 has the recess 40c comprising the bottom surface 40a and the side surface 40b formed therein, and the second resin molding 50 is placed in the recess 40c.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a molding compound surrounding the semiconductor substrate, the conductive pad and the conductor. In the semiconductor device, the conductor has a stud shape.

Abstract: An electronic package includes a lead frame structure having one or more structural features configured to improve board level reliability. In one embodiment, the structural feature comprises lead frame protrusions extending outward from the electronic package, which are configured to laterally engage solder structures used to attach the electronic package to a next level of assembly. In another embodiment, conductive bumps are attached to exposed portions of the lead frame in advance of next level assembly processes. In a further embodiment, the lead frame comprises laterally separated contact points for attaching an electron die and for attaching the electronic package to a next level of assembly.