Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.

Abstract: A packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor.

Abstract: A solid state lighting package is provided. The package comprising at least one LED element positioned on a top surface of a substrate and a conformal reflective layer of inorganic particles, whereby at least of portion of the light emitted by the LED element is reflected by the conformal reflective layer. A method of manufacturing a solid state lighting package comprising the distribution of inorganic particles, and a method of increasing the luminous flux thereof, is also provided.

Abstract: A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: forming a crystalline buffer layer situated at least partly in the trench in the masking layer, extending from the substrate and forming a projection beyond the masking layer so that an upper part of the lateral flanks of said buffer layer is left uncovered, the formation step comprising a growth of the buffer layer from the substrate, and forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered.

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.

Abstract: A semiconductor device includes a first barrier layer having a barrier property against oxygen and hydrogen over a substrate, a first insulator over the first barrier layer, a second insulator over the first insulator, a third insulator over the second insulator, a transistor including an oxide semiconductor over the third insulator, a fourth insulator including an oxygen-excess region over the transistor, and a second barrier layer having a barrier property against oxygen and hydrogen over the fourth insulator. The transistor includes a first conductor with oxidation resistance, a second conductor with oxidation resistance, and a third conductor with oxidation resistance, the second insulator includes a high-k material, the first barrier layer and the second barrier layer are in contact with each other in an outer edge of a region where the transistor is provided, and the transistor is surrounded by the first barrier layer and the second barrier layer.

Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing method, and a display device. The method for manufacturing the TFT includes a step of forming a pattern of a semiconductor active layer on a transparent substrate through a patterning process, and the pattern of the semiconductor active layer includes a lanthanum boride pattern.

Abstract: An integrated circuit structure may include an alignment column on a front-side surface of an isolation layer. The alignment column may extend through a backside surface opposite the front-side surface of the isolation layer. The integrated circuit structure may also include front-side transistors on the front-side surface of the isolation layer. The integrated circuit structure may further include backside transistors on the backside surface of the isolation layer. A first front-side transistor is aligned with a first backside transistor according to the alignment column.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection.

Abstract: An error identification method of a machine tool includes an initial position measurement step of indexing a main spindle head rotation axis to an initial angle to measure an initial position of a measured jig, a table reference angle calculation step of calculating a reference angle of the table, a reference position measurement step of indexing the table rotation axis to the reference angle and indexing the main spindle head rotation axis to the initial angle, a relative position measurement step of respectively indexing the table rotation axis and the main spindle head rotation axis to a plurality of predetermined angles, an arc approximation step of approximating the plurality of measured position values into an arc, and an error calculation step of calculating an error of a center position of the rotation axis, a tilt error of the rotation axis, or a tilt error of the translational axis.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a non-volatile memory (NVM) region and a plurality of metal-oxide-semiconductor (MOS) regions. A NVM transistor in the NVM region includes a tunnel dielectric on the substrate, a charge-trapping layer on the tunnel dielectric, and a blocking dielectric comprising a high-k dielectric material over the charge-trapping layer. The plurality of MOS regions include a number of MOS transistors. At least one of the MOS transistors includes a gate dielectric comprising a high-k dielectric material over a surface of the substrate. Generally, the blocking dielectric and the gate dielectric comprise the same high-k dielectric material. Other embodiments are also described.

Abstract: A flexure has a metal support layer, an electric insulating layer laid on a surface of the metal support layer, a wiring layer having a general part laid on a surface of the electric insulating layer and a terminal to provide a conductive connection to an external slider, and a raising structure in a thickness direction of the wiring layer provided to the terminal independently of the metal support layer so that the terminal protrudes from a surface of the general part or has a surface being flush with the surface of the general part.

Abstract: An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body.

Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.

Abstract: A semiconductor device includes a semiconductor substrate that is made of a semiconductor material with a wider band gap than silicon, a field effect transistor, including a front surface element structure, provided on a front surface of the substrate, and a drain electrode having surface contact with the substrate so as to form a Schottky junction between the semiconductor substrate and the drain electrode.

Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.

Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

Abstract: A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (UBM) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (IMC) disposed on the first surface of the UBM layer, a solder bump bonded to the UBM layer with the IMC therebetween, and a barrier layer disposed on the second surface of the UBM layer and substantially preventing the solder bump from being diffused into the second surface of the UBM layer.