Abstract: A surface processing method by blowing submicron particles is disclosed, in which submicron particles are blown against a surface of a work to deposit a layer of the material of the particles on a surface of the work, or etching the surface of the work.The processing method uses blowing air stream containing submicron particles having average particles size ranging between 0.01 and 3.0 .mu.m. The deposition or etching is effected depending on an incident angle of the particles to the surface of work. According to the method deposition of the material can be effected with very high deposition rate and in case of etching very smooth etched surface is obtained.

Abstract: A patternless, self-aligning method of forming a floating gate on a silicon wafer having a plurality of raised field oxide isolation structures. The method of the present invention includes depositing a polysilicon layer onto the silicon wafer and the raised field oxide isolation structures, depositing a polysilicon etch masking layer onto the polysilicon layer, and planarizing the polysilicon etch masking layer. The polysilicon etch masking layer is then etched to expose the polysilicon layer over the raised field oxide isolation structures. The exposed polysilicon layer is then etched to remove the polysilicon layer over the raised field oxide isolation structures. The remaining polysilicon etch masking layer is then removed, leaving a plurality of polysilicon regions covering the silicon wafer between the field oxide isolation structures.

Abstract: A process for preparing a silicon melt from a polysilicon charge, for use in the production of single crystal silicon ingots by the Czochralski method, in a crucible which has a bottom, a sidewall formation, a centerline which is substantially parallel to the sidewall formation and which intersects a geometric centerpoint of the bottom, and a radius extending from the centerline to the sidewall formation. In the process, the crucible is loaded with chunk polysilicon to form a charge having a bowl-like shape, wherein initially the load generally slopes radially upwardly and outwardly from the centerline toward the sidewall formation to an apex and then slopes generally downwardly and outwardly from the apex to the sidewall formation. The bowl-shaped chunk polysilicon charge is heated to form a partially melted charge, and granular polysilicon is fed onto the partially melted charge to form a mixed charge of chunk and granular polysilicon.

Abstract: A method is disclosed for micromachining recessed layers (e.g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e.g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e.g. CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate.

Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region in which vacancies are the predominant intrinsic point defect and which is substantially free of agglomerated vacancy intrinsic point defects, wherein the first axially symmetric region comprises the central axis or has a width of at least about 15 mm, and a process for the preparation thereof.

Abstract: An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.

Abstract: In double-side polishing of semiconductor wafers, not only the two main surfaces but also the surface of the edge portion can be polished in one operation with cost reduction and freedom from contamination. An apparatus with twin polishing turn tables is used in the double-side polishing and the inner peripheral edge of each carrier hole formed in a wafer carrier is profiled such that the sectional profile of the inner peripheral edge is substantially the copy of the edge of the wafer placed in the hole.

Abstract: A quartz crucible for use in the preparation of silicon crystals substantially free from crystal void defects and a process for its preparation are disclosed. The crucible is prepared by introducing quartz powder into a rotating mould in an atmosphere containing less than about 0.5% insoluble gases such as argon. The quartz powder accumulates along the inner surface of the mould, and is subsequently heated to fuse the quartz powder to produce the crucible. The gases contained in the bubbles in the resulting crucible are comprised of less than about 0.5% insoluble gases.

Abstract: A method for forming a contact hole in a phosphosilicate glass layer includes the steps of forming a phosphosilicate glass layer, reflowing the phosphosilicate glass layer, removing a surface portion of the phosphosilicate glass layer, and forming the contact hole in the phosphosilicate glass layer. In particular, the surface portion of the phosphosilicate glass layer can be on the order of about 1000 .ANG. thick, and the step of removing the surface portion can include etching the surface portion. Furthermore, the step of forming the contact hole can include the step of selectively wet etching the phosphosilicate glass layer followed by the step of selectively dry etching the phosphosilicate glass layer.

Abstract: An electrode is disposed at the lower end of a radiation screen. The electrode is made of single-crystal silicon. A circuit including a power source is established by contacting the electrode and the seed crystal to a silicon melt.

Abstract: An etching process for DUV photolithography is provided for etching a layer of anti-reflection coating (ARC) comprising spin-on organic ARC material which is formed beneath a layer of photoresist. After patterning the layer of photoresist, the layer of ARC is etched by employing a mixture of oxygen plasma, nitrogen plasma, and at least one inert gas. Anisotropic etching of the layer of ARC is provided with the process of the present invention. In comparison with prior art etching processes for etching a layer of ARC, the process of the present invention provides a favorable etch rate with improved selectivity over the etching of the layer of photoresist. The layer of ARC is etched without causing lateral erosion of the layer of photoresist. Faceting of the top edges of the corners of the layer of photoresist is also minimized. The profile of the layer of photoresist is essentially maintained thereby enabling for critical dimension fidelity.

Abstract: To an electroless nickel plating solution comprising a water-soluble nickel salt, a reducing agent, and a complexing agent is added a polythionate or dithionite. The invention also provides a high-build electroless gold plating method comprising the steps of immersing a workpiece in the electroless nickel plating bath, thereby chemically depositing a nickel coating on the workpiece, and immersing the nickel-plated workpiece in an electroless gold plating bath, thereby chemically depositing a gold coating on the workpiece.

Abstract: A method for etching dielectric layers is disclosed. A first etch of the dielectric layers is performed with a gas chemistry comprising C.sub.4 F.sub.8 flowing at about 10 sccm to about 25 sccm and CH.sub.3 F flowing at about 5 sccm to about 20 sccm. A second etch of the dielectric layers is performed with the gas chemistry and flow rates of gases which are about 10% to about 40% greater than the flow rates of gases in the first etch.

Abstract: A method for removing from a patterned silicon containing dielectric layer a patterned partially fluorinated photoresist layer employed in patterning the patterned silicon containing dielectric layer. There is first formed over a semiconductor substrate a metal contact layer having a silicon containing dielectric layer formed thereover. There is then formed upon the silicon containing dielectric layer a patterned photoresist layer. There is then formed by use of a reactive ion etch (RIE) plasma etch method employing a fluorine containing etchant a via through the silicon containing dielectric layer to form a patterned silicon containing dielectric layer reaching the metal contact layer.

Abstract: A wet etching station and a wet etching method adapted for utilizing the same are provided. The wet etching station includes a bath apparatus containing a chemical etchant, with the bath apparatus having a plurality of cooling lines installed in the lower portion of the bath area, such that the cooling lines can make contact with the chemical etchant. Thus, a large-diameter wafer can uniformly etched.

Abstract: A process for etching the sides of a trace remove the feet which extend laterally out from the sides and over a circuit board substrate adjacent the trace.

Abstract: A method for forming an electrode for an integrated circuit device includes the steps of forming a first insulating layer on a semiconductor substrate and forming a conductive mesa on the first insulating layer. The insulating layer has a contact hole therein exposing a portion of the substrate, and the conductive mesa covers and extends into the contact hole so that the conductive mesa is electrically connected to the substrate. A second insulating layer is formed on the first insulating layer wherein the second insulating layer surrounds the conductive mesa and wherein the second insulating layer has a second thickness greater than the first thickness. Accordingly, sidewalls of the second insulating layer are exposed adjacent the conductive mesa. Spacers are formed on the conductive mesa along the sidewalls of the second insulating layer, and the conductive mesa is etched using the second insulating layer and the spacers as an etching mask.

Abstract: The present invention relates to an article of manufacture or polishing pad for altering a surface of a workpiece, such as polishing or planarizing a semiconductor device. The article includes a polymeric matrix impregnated with a plurality of polymeric microelements, each polymeric microelement having a void space therein. The article has a work surface and a subsurface proximate to the work surface. When the article is in contact with a working environment, polymeric microelements at the work surface of the article are less rigid than polymeric elements embedded in the subsurface. As the work surface of the article is abraded during use, the work surface of the pad may be continuously regenerated. In alternative preferred embodiments, the work surface may further include a minitexture and/or a macrotexture. Preferably, the minitexture is formed by fractal patterning at least a portion of the work surface.

Abstract: A semiconductor device manufacturing method includes an etching process or a surface-treating process in which an etching gas or a surface-treating gas including an acyl-group-containing compound represented by the following formula (1):RCOX (1)is used to form a sturdy film on the etched or treated surface, and high anti-resist selectivity, high anti-base-layer selectivity and high plasma-tolerance are thereby achieved, wherein R is an aliphatic hydrocarbon group, an aromatic hydrocarbon group, or a derivative thereof, and X is a substituent. Preferably, the substituent X in the above formula (1) is a halogen atom or a group represented by the following formula (2):R'COO-- (2)wherein R' is an aliphatic hydrocarbon group, an aromatic hydrocarbon group, or a derivative thereof.

Abstract: A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.