Patents Examined by Benjamin Utech
  • Patent number: 5896870
    Abstract: Disclosed is a method and apparatus for polishing a semiconductor wafer. This invention describes a novel in situ method for eliminating residual slurry and slurry abrasive particles on the wafer. A reactant is added to the slurry during the end of the Chemical Mechanical Polish (CMP) process to dissolve the slurry and etch the abrasive particles.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: April 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Cuc K. Huynh, Harold G. Linde, Patricia E. Marmillion, Anthony M. Palagonia, Bernadette A. Pierson, Matthew J. Rutten
  • Patent number: 5891523
    Abstract: The invention provides a method for the metallizing of precision machine parts coupled with heat-treatment and machining to insure the minimal handling the remachining generally required due to dimensional distortion resulting from the standard heat-treatment used in hardening the metallized coating.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: April 6, 1999
    Assignee: Surface Technology, Inc.
    Inventor: Nathan Feldstein
  • Patent number: 5891241
    Abstract: Hydrogenated amorphous carbon mainly composed of sp.sup.3 structure is prepared by adding hydrogen to carbon or decomposing hydrogenated carbon gas, and then rapidly cooling the mixed or decomposed gas on a substrate. The hydrogenated amorphous carbon is irradiated with X rays to excite electrons on the 1s shells of carbon atoms. The carbon atoms are rendered to a state excited with 2.sup.+ ion due to Auger effect caused by the exciation, so as to form atomic vacancies and interlattice atomic couples. The hydrogenated amorphous carbon is then annealed, and carbon atoms are rearranged to rotated triangular pattern. Thus, diamond good of crystallinity useful as a high-temperature semiconductor device, ultraviolet laser diode or protective film can be synthesized at a relatively low temperature and a low pressure. The process is applicable for the growth of a diamond single crystal thin film on a single crystal substrate such as amorphous carbon, silicon, or a Group III-V or II-VI compound semiconductor.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: April 6, 1999
    Assignee: Research Development Corporation of Japan
    Inventor: Hiroshi Yoshida
  • Patent number: 5891807
    Abstract: A method for forming a bottle shaped trench 20 in a semiconductor substrate 10 includes reactive ion etching a trench having a tapered top portion 25 in the semiconductor device and continuing to reactive ion etch while increasing the temperature of the semiconductor device to impart a reentrant profile 22 to the trench.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: April 6, 1999
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: K. Paul Muller, Rajiv M. Ranade, Stefan Schmitz
  • Patent number: 5891353
    Abstract: A semiconductor wafer polishing agent contains mainly a silica containing polishing agent and is added with a polyolefin type fine particle material. The novel semiconductor wafer polishing agent is capable of low brightness polishing to the back face of the wafer, sensor detection of the front and back faces of the wafer, and suppression of dust to be generated by chipping of the back face of the wafer, thereby to increase the yield of semiconductor devices. A polishing method using the polishing agent and a novel semiconductor wafer having a back face with an unconventional surface shape are also disclosed.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: April 6, 1999
    Assignee: Shin-Etsu Handotai Co, Ltd.
    Inventors: Hisashi Masumura, Kiyoshi Suzuki, Hideo Kudo, Teruaki Fukami
  • Patent number: 5890501
    Abstract: Disclosed is a method of dissolving a surface of a semiconductor substrate or a thin-film surface layer formed on the semiconductor substrate, with an oxidizing agent and fluorine-series gas. The method is characterized in that an initial dissolution rate is controlled by gradually increasing a concentration of fluorine-series gas introduced in a dissolving solution containing the oxidizing agent.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: April 6, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minako Kaneko, Ayako Shimazaki, Itsuro Ishizaki
  • Patent number: 5888295
    Abstract: A method of forming a silicon layer having a roughened outer surface includes, a) providing a substantially amorphous silicon layer over a substrate, the amorphous silicon layer having an outer surface; b) providing a seeding layer over the amorphous silicon layer outer surface; and c) annealing the amorphous silicon layer and seeding layer under temperature and pressure conditions effective to transform said amorphous layer into a silicon layer having a roughened outer surface. The amorphous silicon layer is preferably provided by providing a first silicon source gas (i.e., silane) within a chemical vapor deposition reactor under first reactive temperature and pressure conditions effective to deposit a substantially amorphous first silicon layer on the substrate. After the amorphous silicon layer deposition, a second silicon source gas (i.e.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: March 30, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Randhir P.S. Thakur
  • Patent number: 5888905
    Abstract: A intermetal level dielectrics with fluorinated (co)polymers of parylene (142) between metal lines (112-120), and vapor deposition method for the (co)polymerization followed by fluorination of the (co)polymers.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: March 30, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Kelly J. Taylor, Mona Eissa
  • Patent number: 5888296
    Abstract: A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: March 30, 1999
    Assignee: Motorola, Inc.
    Inventors: William J. Ooms, Daniel S. Marshall, Jerald A. Hallmark
  • Patent number: 5888338
    Abstract: The invention provides a novel magnetron plasma processing apparatus comprising the following, a vacuum chamber storing an etching object, the first electrode which is provided in the vacuum chamber and holds the etching object, the second electrode which is disposed in opposition from the first electrode, where the first and second electrodes are in parallel with each other, a gas-supply unit feeding etching gas to the vacuum chamber, a magnetic-field generating means which is disposed on the part opposite from the first electrode in opposition from the second electrode, and a power-supply unit which feeds power to either of these first and second electrodes and generates discharge between these parallel electrodes. Magnetic-field generating means is provided with a magnetic block whose both-end surfaces are provided with magnetic poles having polarity inverse from each other, and in addition, a plane recess opposite from the second electrode is provided between both-end surfaces of the magnetic block.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: March 30, 1999
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Hiromi Harada, Sinji Kubota, Hiromi Kumagai, Junichi Arami, Keiji Horioka, Isahiro Hasegawa, Haruo Okano, Katsuya Okumura, Yukimasa Yoshida
  • Patent number: 5885476
    Abstract: A microetching composition for copper or copper alloys comprising, (a) nitric acid or sulfuric acid, or both, (b) ferric nitrate or ferric sulfate, or both, (c) at least one component selected from a group consisting of unsaturated carboxylic acids, salts of unsaturated carboxylic acid, and anhydrides of unsaturated carboxylic acid, and (d) water. The composition can produce a copper or copper alloy surface exhibiting excellent adhesion to resins such as prepregs and resists and superior solderability. The composition is suitable for the manufacture of printed wiring boards with highly integrated fine line patterns.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: March 23, 1999
    Assignee: MEC Co., Ltd.
    Inventors: Yoong-koo Hong, Toshiko Nakagawa
  • Patent number: 5885347
    Abstract: The object of this invention is to provide a method and a device for manufacturing semiconductor single crystals by the CZ method in response to the increase in the weight of semiconductor single crystal produced. The necked portion formed beneath the reduced portion can be held and the single crystal under lifting can be re-melted.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: March 23, 1999
    Assignee: Komatsu, Ltd.
    Inventors: Junsuke Tomioka, Hiroshi Inagaki, Ayumi Suda, Toshimichi Kubota
  • Patent number: 5885903
    Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: March 23, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Whonchee Lee
  • Patent number: 5885477
    Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: March 23, 1999
    Assignee: Micron Display Technology, Inc.
    Inventors: Robert T. Rasmussen, Surjit S. Chadha, David A. Cathey
  • Patent number: 5885888
    Abstract: An etching material comprising at least phosphoric acid, acetic acid, and nitric acid, with chromic acid added therein. Also claimed is an etching process using the etching material above, provided that the process comprises selectively etching, by using the solution, an aluminum oxide layer formed on the surface of a material containing aluminum as the principal component thereof.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: March 23, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara
  • Patent number: 5883006
    Abstract: A method of forming an opening in a first film is provided, wherein the opening has first and second opening portions and the first film is an insulating film. The first opening portion is formed in the first film and a second film is formed on an upper surface of the first film and to fill in the first opening portion. A masking film is formed on the second film. The first film and the second film are etched by a first etching process using the masking film as a mask to form the second opening portion. The first film and the second film are etched at substantially the same rate by the first etching process. The remaining portion of the second film in the first opening portion is etched by a second etching process. The second film is etched at a higher rate than the first film by the second etching process.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: March 16, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junichiro Iba
  • Patent number: 5880037
    Abstract: A method of plasma etching oxide in the presence of nitride includes contacting the oxide with a mixture of gases including one or more flourine-substituted hydrocarbon etching gases and acetylene. The method exhibits high selectivity to nitride, including nitride on uneven surfaces.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: March 9, 1999
    Assignee: Applied Materials, Inc.
    Inventor: Paul Arleo
  • Patent number: 5880035
    Abstract: An object of this invention is to provide a dry etching method enabling a higher productivity and a higher yield without giving any bad effect to a substrate (such as, for instance, damages to a gate oxide film bed) even in a case where a side wall protection film is formed and then the side wall protection film must be removed later.This invention is a dry etching method for processing a polycide layer, in which a poly Si layer and a refractory metal silicide layer are formed in this order on an oxide film bed, by etching resist patterns selectively formed on said polycide layer into a mask, wherein the undercut 6 is provided in the refractory metal silicide layer 2 or other layers contacting the resist pattern 1 and then the refractory metal silicide layer 2 and the poly Si layer 3 are isotropically etched.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: March 9, 1999
    Assignee: Sony Corporation
    Inventor: Seiichi Fukuda
  • Patent number: 5880028
    Abstract: A ridge waveguide type distributed feedback semiconductor laser device includes a diffraction grating formed on a surface of a semiconductor wafer, a semiconductor layer formed on the diffraction grating, the semiconductor layer serving to alleviate the irregularity of the diffraction grating, and a stripe-like ridge having a cladding layer and a contact layer formed on the semiconductor layer. Also, a method for manufacturing the ridge waveguide type distributed feedback semiconductor laser device is disclosed.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: March 9, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kei Yamamoto, Takuma Hiramatsu, Koji Takahashi, Mototaka Taneya
  • Patent number: 5872061
    Abstract: A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: February 16, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Long Lee, Chia Shiung Tsai, So Wein Kuo