Abstract: The use of selected cation exchange resins to remove dissolved multivalent cations ions such as iron, zinc, and chromium from used autodeposition compositions permits reuse of the autodeposition compositions without the need for added surfactant and without developing any undesirable graininess or other texture in the coatings formed. Iminodiacetate cation exchange resins are very effective for removing iron ions when they are the only multivalent ions to be removed, and can be efficiently regenerated with 0.5 to 4% by weight aqueous hydrofluoric acid. By proper choice of other cation exchange resins and operating conditions, zinc can be selectively extracted from autodeposition baths containing both iron and zinc, and either iron or zinc can be selectively displaced from the loaded ion exchange resin.

Abstract: A chemical mechanical planarization tool that reduces a volume of polishing chemistry used in a wafer polishing process includes a rinse bar (87) for removing polishing chemistry and particulates from a polishing media and a slurry measurement system (84) for regulating a pump (83) of a slurry delivery system. A volume of the slurry delivery system is reduced to less than 100 milliliters. Approximately a minimum volume of polishing chemistry for polishing a single wafer is dispensed during each wafer polishing process of a wafer lot. During each wafer polishing process the slurry delivery system is purged to prevent settling, agglomeration, and hardening of the polishing chemistry. The rinse bar (87) sprays a surface of the polishing media to remove spent polishing chemistry and particulates prior to polishing another semiconductor wafer.

Abstract: A wafer on which a GaAs layer is disposed on an Al.sub.x Ga.sub.1-x As (0<x.ltoreq.1) layer. An etching mask is formed on the GaAs layer. An etching gas containing chlorine, oxygen, and nitrogen is fed into a reaction chamber to generate a plasma having a plasma density of 10.sup.10 cm.sup.-3 or more, and the GaAs layer is etched using the Al.sub.x Ga.sub.1-x As layer of the wafer as an etching stop layer. This selective etching method is applied to formation of a gate recess structure in a compound semiconductor device.

Abstract: According to the invention, the flatness and quality can be improved while simplifying the process even when large size wafers of 200 to 300 mm or above are processed. Basic steps involved are a slicing step E for obtaining thin disc-shape wafers by slicing, a chamfering step F for chamfering the sliced wafers, a flattening step G for flattening the chamfered wafers, an alkali etching step H for removing process damage layers from the flattened wafers, and a double-side polishing step K of simultaneously polishing the two sides of the etched wafers. If necessary, a plasma etching step is used in lieu of the flattening and etching steps G and H respectively.

Abstract: A method of fabricating a semiconductor device includes the steps of sequentially forming a gate oxide layer, a gate material layer and a cap insulating layer on a semiconductor substrate, selectively etching them to form a gate, sequentially forming a plurality of material layers on the overall surface of the semiconductor substrate including the gate, etching them back to form a gate sidewall spacer out of the plurality of material layers, and selectively removing the plurality of material layers forming the gate sidewall spacer to form gate sidewall spacers having lengths different from each other, the lengths depending on a particular region of the substrate.

Abstract: The method of evaluating silicon wafers according to this invention is capable of predicating degradation of the quality of oxide film insulation, which is incurred, on the silicon wafers, by process faults or local residual strains undetectable by the naked eye. The method includes the following steps of: removing selectively a surface of a silicon wafer treated by mirror polishing by using an etching selectivity caused by an unordinary surface state; counting the number of etch pits on the surface of the silicon wafer with the aid of an optical microscope; and judging the quality of the silicon wafer based on the etch pit density, which is calculated from the above number of etch pits, and the threshold value of etch pit density. The threshold value of etch pit density of the silicon wafer treated by selective etching is set to be below 5.times.10.sup.5 pits/cm.sup.2, and improvements to the processing of production lines relating to low-quality silicon wafers can be made.

Abstract: A method for forming a microelectronic capacitor includes the steps of forming a first conductive layer on a substrate and forming an oxide reducing layer on the first conductive layer opposite the substrate wherein the oxide reducing layer reduces oxidation of the first conductive layer. An oxide layer is formed on the oxide reducing layer opposite the substrate, and a dielectric layer is formed on the oxide layer opposite the substrate wherein the dielectric layer has a dielectric constant that is higher than a dielectric constant of the oxide reducing layer, and higher than a dielectric constant of the oxide layer. In addition, a second conductive layer is formed on the dielectric layer opposite the substrate. Related structures are also discussed.

Abstract: Compositions of ammonium fluoride, propylene glycol, and water and methods of using these compositions to remove etch residues from silicon substrates which result from plasma or reactive ion etching of silicon substrate are provided. Not only do the compositions of the present invention overcome the environmental concerns associated with the use of ethylene glycol, but unlike previous compositions of ammonium fluoride in propylene glycol which are acidic, the compositions of the present invention are neutral to slightly basic (i.e., pH 7 to about pH 8). Hence, they remove etch residues from silicon substrates with minimal attack on other features on the silicon substrates.

Abstract: A method for preparing a sample for TEM is described. The method is particularly well suited for examining the active region of an FET. After removing the various layers present above the active region, the polysilicon gate is exposed and then selectively removed. In a key feature of the invention, care is taken to ensure that the regions of field oxide on either side of the active region are left fully intact. After using a laser to mark the area of interest for later ease of identifcation, the silicon is etched down to a few thousand Angstroms, followed by ion milling to further reduce the thickness over the area of interest. Because of the support provided by the field oxide, very thin layers can be exposed without the danger of them pulling away from the silicon.

Abstract: A method for etching a trench in a monocrystal silicon layer. The method includes providing a plasma processing system having a plasma processing chamber. The plasma processing system has a variable plasma generation source and a variable ion energy source with the variable plasma generation source being configured to be controlled independently of the variable ion energy source. The method further includes flowing an etchant source gas that includes O.sub.2, helium, and at least one of SF.sub.6 and NF.sub.3 into the plasma processing chamber. There is also included energizing both the variable plasma generation source and the variable ion energy source to form a plasma from the etchant source gas. Additionally, there is included employing the plasma to etch the trench.

Abstract: An apparatus for forming I-III-VI.sub.2 thin-film layers has a reaction chamber made of a carbon material in which a precursor for forming a I-III-VI.sub.2 thin-film layer and a vapor source of an element of group VI of the periodic table are placed. The precursor and vapor source are heated under vacuum to form the I-III-VI.sub.2 thin-film layer. The reaction chamber is divided into a reaction compartment A having the precursor placed therein and a reaction compartment B having the vapor element of group IV placed therein. A communication channel C is provided between the reaction compartments A and B, and a heating unit controlled by a temperature control unit is provided exterior to each of the reaction compartments A and B.

Abstract: A zinc phosphate conversion coating which is accelerated only with nitrogen free organic peroxides is low-polluting and able to form uniform, fine, and dense conversion coatings that exhibit an excellent paint adherence when thin and excellent lubricity/lubricant carrier quality when thick.

Abstract: A method of forming a planar intermetal dielectric over conductive metal structures is disclosed. The method comprises the steps of: (1) forming a liner oxide layer over the conductive metal structures; (2) forming a spin on glass layer over the liner oxide layer; (3) forming a cap oxide layer over the spin on glass layer; (4) forming a TiN layer over the cap oxide layer; (5) patterning and etching a contact hole through the TiN layer using the cap oxide layer as an etching stop; and (6) etching the cap oxide, the spin on glass, and the liner oxide down to the conductive metal structures using the TiN layer as a mask.

Abstract: Physical properties of alumina particles in a chemical-mechanical polishing slurry delivery loop (28) are measured using a titration technique (44). Examples of the physical properties include crystallographic phase, surface charge, and surface charge density. The physical properties are correlated to a polishing rate (46). Specification limits are generated using the correlated data (482 and 486). The specification limits are used to determine if no adjustments are required to the polishing parameters (484), if adjustments are required to polishing parameters (488) or if the slurry requires replacement (489). This process can be automated and integrated into a conventional chemical-mechanical polishing processing system (20).

Abstract: A thin glaze layer 2 is formed on a relief surface 1R to a thickness which leaves recesses on the relief surface 1R. A glaze-repellent layer 4 capable of repelling the glaze slurry is then formed on the surface of the thin glaze layer 2 to form a coated substrate. The glaze slurry is affixed to the coated substrate for forming a glaze slurry layer 5 for completing the glazing.With the conventional method for producing a ceramic article or for glazing, it has been extremely difficult to produce a ceramic article having a relief pattern of beautiful appearance, that is a ceramic article glazed to a sufficient thickness and presenting clearly defined crests and valleys of the relief pattern.

Abstract: A method for trench filling during integrated circuit manufacture is described in which the filled-in surface is dishing inhibited. To accomplish this an extra layer is introduced between the trench-defining mask material and the trench filler material. This transition layer is characterized by having a removal rate (under CMP) that is greater than that of both the mask material and the filler material. An important additional advantage is that end-point detection is now much easier because of the large difference in removal rates between the mask and transition layers.

Abstract: Fabrication of devices that produces a surface with reduced dishing caused by polishing. The reduced dishing is the result of forming a first layer that partially covers a complex surface topography and a second layer the covers the surface topography. The second layer being more resistant to polishing than the first so as to reduce dishing in the wide spaces of the complex topography.

Abstract: A method for making a stacked gate electrode structure for a semiconductor device provides for three layers of the stacked structure including a first conductive layer, an insulating layer, and a second conductive layer. The layers of the stacked structure are to be of uniform width. The method includes forming on a gate oxide layer on the surface of the semiconductor substrate a first conductive layer, an insulating layer, and a second conductive layer in order. A photoresist is formed on the second conductive layer and patterning of the second conductive layer and the insulating layer using the photoresist as an etching mask is carried out. Side wall covering layers which result from the insulating layer patterning which cover the sides of both the second conductive layer and the insulating layer are removed. Thereafter, the first conductive layer is patterned using the photoresist as an etching mask.

Abstract: A composition and method for stripping tin or tin-lead alloys, and any underlying copper-tin intermetallic, from a copper surface. The composition includes an aqueous solution of approximately 5-60% nitric acid by weight, approximately 0.5-30% ferric nitrate by weight, and a nitric acid stabilizer selected from the group consisting of an amino-triazole, an amino-isoxazole, and a linear amino sulfone in the form H.sub.2 N-SO.sub.2 -R, where R is any alkyl or benzene group, wherein the stabilizer is present at a concentration sufficient to inhibit exothermic conditions, emission of toxic NOx gas, and copper attack. A soluble source of halogen ion, such as hydrochloric acid, can be added to the composition to yield a uniform, reflective, bright pink copper appearance, and to further reduce sludge formation. In addition, sludge formation can be eliminated by adding a soluble source of sulfate ion (SO.sub.4.sup.-2) to the composition.

Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7.