Patents Examined by Bot L. Ledynh
  • Patent number: 5644468
    Abstract: An X-Y condenser having an X-capacitance and two Y-capacitances, for example, for connection as a line filter, has a base winding of metallized dielectric foil strip on which a pair of axially spaced auxiliary windings are applied. A deposited metal contact at each end connects each Y-capacitance winding with the X-capacitance winding while a metal deposit between the Y-capacitance windings forms a common contact therewith.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: July 1, 1997
    Assignee: Eichhoff GmbH
    Inventors: Reinhold Wink, Mathias Gruner
  • Patent number: 5644102
    Abstract: A technique is described for providing body coloration and colored indicia for indicating one or more characteristics of an integrated circuit device. Package body coloration is one source of information about device characteristics. Other indications relate to colored indicia. The colored indicia are relatively large and easily viewable from distances too great for printed text on the package body to be read comfortably. The indicia is (are) colored other than black or white. Among the visible indicia characteristics which can be used to convey information are: indicia color (or colors on multi-colored indicia), shape, size, orientation, and/or location. Among the various integrated circuit device characteristics which can be conveyed by the indicia characteristics are: device function, device speed, level of testing, degree of rad-hardness, location of reference pin, side, corner or surface, location and function of groups of pins carrying related signals, etc.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: July 1, 1997
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rostoker
  • Patent number: 5644103
    Abstract: A structure includes a baseplate, a circuit board parallel and adjacent to the baseplate, and an electronic component. The circuit board has an edge with a scallop formed in the edge, and the scallop is plated with a conductive material. The electronic component includes a power-dissipating surface and a pad for making electrical connection. The electronic component is mounted with the power-dissipating surface in contact with the baseplate and the pad electrically connected to the conductive material.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: July 1, 1997
    Assignee: VLT Corporation
    Inventors: Stephen R. Pullen, Walter R. Hedlund, III
  • Patent number: 5644101
    Abstract: A shield assembly for installation on a portion of a printed circuit board is presented. The shield (16) assembly includes shield mounted on the component mounting side of the printed circuit board and has a plurality of support projections (30) inserted through apertures of the printed circuit board to the conductor side where they are mechanically secured and electrically connected to a reference potential. A first shield cover (22) is mounted to the shield at a peripheral edge distal of the printed circuit board. A second shield cover (34) is disposed at the conductor side of the printed circuit board. The second shield cover (34) is provided with two pluralities of protrusions (32, 42). The first plurality of protrusions (32) extends through apertures in the printed circuit board to engage the body of the shield. The second plurality of protrusions (42) engages respective support projections (30) of the shield.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: July 1, 1997
    Assignee: Thomson Consumer Electronics, Inc.
    Inventor: Charles Anthony Elliott
  • Patent number: 5642255
    Abstract: A hollow cylindrical resin case provided at a periphery thereof with an axial opening and a resin terminal plate, one of which has a concave coupling section and the other has a convex coupling section, are coupled together and then filler resin is injected between the capacitor element attached to the terminal plate and the resin case to provide a seal. One or both of the resin case and the resin terminal plate are made of thermoplastic resin, and a space is defined between the coupling sections. A dimension of the space and an inserting force applied to the coupling portions are set to appropriate values, thereby realizing a high quality capacitor free from leakage of filler resin.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: June 24, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuji Suzuki, Mitsumasa Oku
  • Patent number: 5641941
    Abstract: A method and apparatus for operably connecting electronic devices through a closed container is achieved by securing one end of a laminate connector (28) to a first electronic device, e.g., a fireset circuit (22). Device (22) is placed in a housing (12) which defines a housing closure surface (16). A cover (14a), which defines a cover closure surface (18) dimensioned and configured to engage the housing closure surface (16), is placed on the housing (12) to define a housing-cover joint (20a), and the laminate connector (28) is disposed within the housing-cover joint (20a). The housing-cover joint (20a) is sealed with an adhesive and the second end of the laminate connector (28) is connected to a second electronic device. The thinness of the laminate connector allows it to pass through the housing-cover joint (20a) without significant adverse affect on the seal therein or on the pressure-bearing ability of the housing (12) or the cover (14a).
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: June 24, 1997
    Assignee: The Ensign-Bickford Company
    Inventors: Charles A. Dieman, Jr., Andrew C. Johnsen
  • Patent number: 5639990
    Abstract: The present invention relates to a solid printed substrate to be used for mounting electronic parts and a method of manufacturing the same. A metal base substrate having a plurality of copper foil layers stacked thereon is employed placing a thermoplastic polyimide sheet between each copper foil. The metal base substrate with a circuit pattern prepared on each copper foil layer is processed by bending or deep drawing into a box-shaped work which has an opening surface. The opening surface is processed so as to have a substantially equal area with that of the bottom of the substrate and have a collar portion on the periphery thereof. On the collar portion, leads to be used for connection with other wiring substrate are formed by patterning on copper foil layers.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: June 17, 1997
    Assignee: Mitsui Toatsu Chemicals, Inc.
    Inventors: Kunio Nishihara, Youichi Hosono, Kunihiro Nagamine, Takashi Kayama, Takayuki Ishikawa
  • Patent number: 5637828
    Abstract: The invention discloses a high density semiconductor package. Two semiconductor chips are each affixed on a corresponding one of two lead frames. The semiconductor chips and the lead frames are encapsulated, wherein only a portion of the leads of the lead frames protrudes and extends from the package.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 10, 1997
    Assignee: Texas Instruments Inc.
    Inventors: Ernest J. Russell, Daniel A. Baudouin, Duy-Loan T. Le, James Wallace
  • Patent number: 5638250
    Abstract: A capacitor which is provided with internal protection and in which plastic film is wound around a core tube (3) to form a capacitor cylinder (2). Metallic contact surfaces (4, 5) are formed at the ends of the cylinder to connect connecting leads, and a fusible portion (9) is provided between the second contact surface (5) and the phase lead, said fusible portion (9) serving both as a thermal fuse and as an overload protector.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: June 10, 1997
    Assignee: Nokia Kondensaattorit Oy
    Inventor: Hans Oravala
  • Patent number: 5635671
    Abstract: According to the invention, an electronic device mounted on a substrate is encapsulated using a standard two-piece mold. A novel degating region is formed on a surface of the substrate to allow removal of excess encapsulant formed on the surface during molding without damaging the remainder of the device. The material of the degating region that contacts the encapsulant forms a weak bond with the encapsulant, relative to the bond formed between the encapsulant and the substrate, so that the encapsulant can be peeled away from the degating region without damaging the substrate or other portion of the device. The degating region is provided without introducing additional steps into the process for forming the device. The presence of the degating region eliminates the necessity of using a three-piece or modified two-piece mold to achieve top gating in order to degate without damaging the device. In one embodiment, the degating region is made of gold.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: June 3, 1997
    Assignees: Amkor Electronics, Inc., Anam Industrial Co., Ltd.
    Inventors: Bruce J. Freyman, John Briar, Young W. Heo, Il K. Shim
  • Patent number: 5633781
    Abstract: A capacitor structure is provided, with a first conductor on top of a substrate having at least one layer of dielectric material thereon; a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein; a second conductor, in electrical contact with the first conductor, formed on the sidewalls of the first opening; a non-conductive sidewall spacer formed in the first opening and contacting the second conductor, the non-conductive sidewall spacer having a second opening formed therein; and a third conductor formed in the second opening.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Katherine L. Saenger, David E. Kotecki
  • Patent number: 5631193
    Abstract: The present invention provides a method and apparatus for fabricating thermally and electrically improved electronic integrated circuits by laminating one or more lead frames to a standard integrated circuit package such as, for example, a thin small outline package (TSOP). The lead frame laminated to the package enhances thermal conduction of heat from the integrated circuit package. A heat spreader may also be utilized to improve heat transfer and can be further used as a ground plane to improve signal quality by reducing electrical circuit noise. Achieving improved thermal transfer characteristics from an integrated circuit package results in better dissipation of heat from the integrated circuit package and results in more reliable operation thereby. Using standard commercially available integrated circuit packages such as TSOP allows economical and rapid fabrication of thermally and electrically superior electronic circuits for applications that demand high reliability and performance.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: May 20, 1997
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5627730
    Abstract: A printed circuit board assembly which includes a two-dimensional array of connectors to provide significantly higher data transfer rates than typical one-dimensional connectors, without sacrificing board space. The assembly preferably includes a plurality of connection pads on each printed circuit board. An anisotropically conducting material is placed between the connection pads and the boards pressed together.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: May 6, 1997
    Assignee: NCR Corporation
    Inventors: Walter Konig, Albert Modl, Peter F. Baur
  • Patent number: 5623123
    Abstract: Semiconductor device package 53 having a lead frame with a mounting pad 31 smaller than the IC chip 10 mounted thereon, and a method of making a semiconductor device package based on wire bonding using a heater insert 38 with a mounting pad insertion concave part 51. Separation between the mounting pad and an encapsulating resin is eliminated, cracks are not created in the resin, or are considerably reduced, and warpage of the package can be prevented. Also, bonding of wires between leads and respective bonding pads 17 on the chip 10can be executed stably and efficiently.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: April 22, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Norito Umehara
  • Patent number: 5621188
    Abstract: A shielding medium using a multi-layered construction for protection of an object such as the human body, with each layer containing a plurality of geometrically shaped objects, that appears to the EMFs as a continuous, solid plane, but retains open spaces around the objects for ambient air to circulate. As a result of this construction, the unique shielding medium affords excellent protection against both the electric and magnetic field components of EMFs without sacrificing the comfort of the user (or heat dissipation of the source).
    Type: Grant
    Filed: May 6, 1994
    Date of Patent: April 15, 1997
    Inventors: Sang C. Lee, Bak H. Lee
  • Patent number: 5621607
    Abstract: A high performance double layer capacitor having an electric double layer formed in the interface between activated carbon and an electrolyte is disclosed. The high performance double layer capacitor includes a pair of aluminum impregnated carbon composite electrodes having an evenly distributed and continuous path of aluminum impregnated within an activated carbon fiber preform saturated with a high performance electrolytic solution. The high performance double layer capacitor is capable of delivering at least 5 Wh/kg of useful energy at power ratings of at least 600 W/kg.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: April 15, 1997
    Assignee: Maxwell Laboratories, Inc.
    Inventors: C. Joseph Farahmandi, John M. Dispennette
  • Patent number: 5621190
    Abstract: In a ceramic package main body having a circuit wiring provided to a ceramic substrate and including first and second independent circuit wires, first and second conductive layers are formed on the ceramic substrate. A first connection wire is provided to connect between the first circuit wire and the first conductive layer. A second connection wire is provided to connect between the second circuit wire and the second conductive layer. The first and second conductive layers are electrically insulated from each other for enabling to examine an electrical connection between the first and second conductive layers and determine, from the result of the examination, whether a short circuit is developed between the first and second circuit wires.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: April 15, 1997
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kozo Yamasaki, Naomiki Kato
  • Patent number: 5619012
    Abstract: A circuit assembly is made by overmolding, with an electrically insulating material, a unitary framework of electrically conductive material forming coplanar conductors which are connected to each other by an integral structural member. The overmolded material secures the conductors relative to each other and enables portions of the structural member to be severed, electrically isolating the conductors from each other. The overmolded material also positions electrical components having leads that are electrically connected to the conductors. Ends of the conductors are formed into terminals which extend out of a hinge formed in the overmolded material. The hinge enables the terminals to be oriented in a different plane than the conductors.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: April 8, 1997
    Assignee: Philips Electronics North America Corporation
    Inventors: David C. Casali, John E. Opie, Solomon Fridman
  • Patent number: 5617290
    Abstract: A semiconductor device and process for making the same are disclosed which incorporate boron, which has been found to be substantially insoluble in BST, into a BST dielectric film 24. Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Boron included in a BST precursor may be used to form boron oxide in a second phase 30, which is distributed in boundary regions between BST crystals 28 in film 24. It is believed that the inclusion of boron allows for BST grains of a desired size to be formed at lower temperature, and also reduces the leakage current of the capacitive structure.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 1, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Bernard M. Kulwicki, Robert Tsu
  • Patent number: RE35496
    Abstract: A semiconductor device of the present invention accommodates a large semiconductor chip in a downsized package without impairing its reliability. The semiconductor chip is bonded on a relatively small die pad. Common inner leads and a plurality of inner leads are disposed opposite and spaced from the semiconductor chip by a gap ranging from 0.1 mm to 0.4 mm and the gap between the semiconductor chip and the common inner leads and the plurality of inner leads is filled with a resin which forms pan of a resin package.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: April 29, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ken Yamamura, Naoto Ueda, Kazunari Michii, Hitoshi Fujimoto, Kiyoaki Tsumura, Hitoshi Sasaki, Takashi Miyamoto