Patents Examined by Bot L. Ledynh
  • Patent number: 5598317
    Abstract: A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patterning an area of the conductive thin film. Laser patterning is performed by applying the laser along the outer boundary of the area to be patterned to energetically remove the conductive thin film along this boundary.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: January 28, 1997
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ciaran Hanrahan, Andrew P. Stack
  • Patent number: 5597979
    Abstract: An electronic device is shielded against electromagnetic interference using a flexible conductive sheet forming a shield barrier or enclosure. The sheet has electrically insulating polymer material exposed on the surface of at least one face. Conductive material is embedded in or laminated on the sheet so as to be exposed selectively. More particularly, a nonconductive surface area is formed, especially oriented inwardly to avoid electrical shorts, but also exposed inwardly or outwardly where necessary to ground the shield barrier or to engage with another conductive body. The flexible sheet can form a loose envelope with a flange-like gasket at an open end. The gasket can be used to improve physical contact with a conductive body, and preferably also admits I/O connectors that need to traverse the shield barrier, and advantageously have external shielding that is grounded to the shielding barrier for continuing the shielding enclosure.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: January 28, 1997
    Assignee: Schlegel Corporation
    Inventors: Daniel T. Courtney, Kenneth W. Hermann, Stanley R. Miska
  • Patent number: 5596170
    Abstract: A flexible electrical contact is formed as a convex dome structure extending from one side of a surrounding structure, with the convex dome structure and the surrounding structure forming an integral metallic structure. The convex dome structure includes a central contact portion and a number of legs extending between the central contact portion and the surrounding structure. Each leg extends radially outward from the central contact portion and circumferentially around part of the central contact portion. A number of convex dome structures of this kind may be part of a removable shield in an electronic enclosure, provided to electrically ground the shield to a conductive frame, reducing the level of RFI (radio frequency interference) emissions from a device. Alternately, a number of convex dome structures may be provided along spring strips fastened to such a shield. In such spring strips, electrical contact may occur between the shield and intermediate positions along the length of the legs.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: January 21, 1997
    Assignee: International Business Machines Corporation
    Inventors: Richard M. Barina, James W. Deiso, III, Arthur A. Kurz, Jeffrey McFadden, Fred L. Murray, William D. Owsley
  • Patent number: 5594200
    Abstract: A glove box enclosing a volume shielded from electromagnetic radiation by the glove box wherein the gloves are formed from conductive material such as chain mail and are conductively and shieldingly attached around apertures in the walls of the glove box, permitting an operator to manipulate directly a device under test within the glove box while maintaining the shielding continuity of the box. A shielded window and an interior light can be included to facilitate viewing of a device within the box during manipulation of the device. The glove box provides an inexpensive, fully-shielded environment for the testing, tuning, adjusting, or repair of RF transmitting or receiving devices such as pagers, electronic notebooks, and cellular telephones.
    Type: Grant
    Filed: June 9, 1995
    Date of Patent: January 14, 1997
    Assignee: Ramsey Electronics, Inc.
    Inventor: John G. Ramsey
  • Patent number: 5594199
    Abstract: An electronic control module includes an EMI baffle in the form of openings formed in laterally spaced portions of the cold plate supporting the electronic circuits. Preferably, upper and lower plates of the cold plate define a limited access baffle chamber with openings that require rerouted travel of any leakage radiation emanated by terminals or conductors carried by couplers inserted into the cold plate openings or passing through the openings. Preferably, each coupler is inserted through openings having an inlet axis in the cold plate and the module packaging covers are secured to the cold plate between an inlet and an outlet opening in the cold plate. Accordingly, simple gaskets may be used to seal the covers against the cold plates and the couplers against the cold plate. Moreover, the cold plate coolant passage has inlets and outlets that remain exposed exteriorly of the covers to avoid exposure of the internal circuitry to leakage.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: January 14, 1997
    Assignee: Ford Motor Company
    Inventor: Michael P. Ciaccio
  • Patent number: 5594204
    Abstract: An apparatus directed to portable peripheral cards is disclosed which provide protection against electro-static discharge and electro-magnetic interference. Furthermore, this apparatus provides a solid housing which affords a strong protective structure for the PC board and also protects the ICs housed inside the peripheral card from being easily accessed.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: January 14, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Carl J. Taylor, Michael W. Patterson, Gordon Force
  • Patent number: 5592359
    Abstract: First and second units have similar, preferably substantially identical, constructions. Each unit is preferably cylindrical and has an outer electrically conductive shell preferably made from a metal. A dielectric material, preferably a ceramic, abuts the inner surface of the electrically conductive shell in each unit. A conductive coating is disposed on the inner surface of the dielectric material in each unit. In this way, each unit defines a capacitor with the shell and the conductive coating constituting the capacitor plates. The shell and the dielectric material in each unit have axially extending openings of matching dispositions. The units are disposed in abutting relationship with the openings facing each other. An alternating voltage is applied between the conductive coating and the conductive shell in each unit. This causes current to flow through the capacitor in each unit and to produce vibrations of the shell and the dielectric material in each unit.
    Type: Grant
    Filed: July 13, 1994
    Date of Patent: January 7, 1997
    Assignee: Undersea Transducer Technology, Inc.
    Inventor: Harry W. Kompanek
  • Patent number: 5588201
    Abstract: For the production of a cast resin coil consisting of a plurality of axially superimposed flat coils, it is proposed that the corresponding flat coils be first of all produced by winding a first inner partial winding and a second outer partial winding with the interposition of individual spacer members by which sector-shaped intervening spaces are formed. The individual flat coils are then placed together axially and oriented so that their intervening spaces coincide, thus forming axial cooling channels. Moldings are inserted into each of said channels. This is followed by the encapsulation of the assembled flat coils. After the curing of the casting resin, the moldings are removed from the cooling channels. A cast resin coil produced in this manner has an impregnable layer of material, preferably in the region of the cooling channels by which the wall thickness of the cooling channels is predetermined in relation to the corresponding strip conductors.
    Type: Grant
    Filed: September 21, 1993
    Date of Patent: December 31, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Friedrich Alber, Rudolf Dedelmahr, Winfried Jungnitz, Hans Schott, Heinz Sesterheim, Siegfried Weiss
  • Patent number: 5590017
    Abstract: An alumina multilayer wiring substrate having a high capacitance in the substrate on which a VLSI is to be mounted to effectively eliminate electrical noise(s) which may hinder the operation of the VLSI at high speed (frequency). The wiring substrate comprises: (a) a first alumina layer; (b) a first metallized layer on the first alumina layer; (c) a dielectric material layer on the first metallized layer; (d) a cermet layer on the dielectric material layer; (e) a second metallization layer on the cermet layer; (f) a second alumina layer on the second metallization layer; (g) a first conductor electrically connecting to and extending from the second metallized layer through the second alumina layer; and (h) a second conductor electrically extending from the first metallized layer through the cermet layer and dielectric material layer, through but not electrically connecting the first metallized layer, and through the second alumina layer.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: December 31, 1996
    Assignee: Aluminum Company of America
    Inventor: John F. Kelso
  • Patent number: 5590029
    Abstract: A space-saving circuit board mounting of a Surface Mounted Technology (SMT) device, such as a resistor, capacitor, ferrite or clock oscillator, is achieved using (1) a single through hole extending transversely through the board substrate, and (2) a cylindrical adapter having a first longitudinal portion coaxially received in the through hole and a second longitudinal portion projecting outwardly therefrom. The second longitudinal adapter portion has a radially inwardly extending notch that receives the SMT device and positions it with its electrically conductive opposite end sections spaced apart in a direction parallel to the axis of the through hole. Spaced apart external metal plating sections on the adapter connect the SMT device end portions to circumferentially separated metal plating segments on the surface of the through hole which, in turn, are representatively connected to ground and signal plane structures within the interior of the board substrate.
    Type: Grant
    Filed: January 12, 1995
    Date of Patent: December 31, 1996
    Assignee: Dell USA, L.P.
    Inventor: H. Scott Estes
  • Patent number: 5587885
    Abstract: To facilitate the registered connection between a laminated multi chip module and an associated multi-tiered circuit board, spaced series of vias are formed transversely through the circuit board and module substrates between their opposite first and second sides. Gold plated BGA leads, offset from the module substrate vias, are formed on the first module substrate side on multi-layer plating structures disposed thereon and extending along the module via interior side surfaces. A spaced series of relatively shallow, circularly cross-sectioned socket areas, offset from the circuit board vias, are also formed on the first side of the circuit board. The sockets have diameters slightly larger that those of the generally ball-shaped BGA leads of the multi chip module, and are positioned on the same centerline pattern as the leads.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: December 24, 1996
    Assignee: Dell USA, L.P.
    Inventor: N. Deepak Swamy
  • Patent number: 5587871
    Abstract: There are disclosed an electrolyte solution for an electrolytic capacitor containing an organic polar solvent and an ionic solute, and further comprising fine particles of an aluminosilicate represented by the following formula, or metal oxide fine particles covered with said aluminosilicate:MAlO.sub.2 (Al.sub.2 O.sub.3).sub.x (SiO.sub.2).sub.ywherein M represents a monovalent cation; x represents a real number of 0 to 25; and y represents a real number of 1 to 200,and an electrolytic capacitor using said electrolyte solution.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: December 24, 1996
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Makoto Ue, Tomohiro Sato, Masayuki Takeda
  • Patent number: 5586008
    Abstract: A latch connected to a surface mount component for subsequent connection to a printed circuit board is provided as well as a method for mounting a surface mount component to a printed circuit board having a zero mounting force. The surface mount component has a soldering tail extending therefrom and at least one latch or latch contact insertable through an aperture in the printed circuit board, without force, such that the soldering tails extending from the surface mount component rest on corresponding soldering pads of the printed circuit board. As a result, surface mount components are mountable to a printed circuit board using standard, available equipment, such as a vacuum head placed component which allow for placement of the component via gravity, and the components are subsequently soldered to the printed circuit board. The assembly also includes a board latch pin and a weighted cap.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: December 17, 1996
    Assignee: Methode Electronics, Inc.
    Inventors: Charles A. Kozel, John Oldendorf, John T. Scheitz, Tuan J. Tan
  • Patent number: 5585016
    Abstract: A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patterning an area of the conductive thin film. Laser patterning is performed by applying the laser along the outer boundary of the area to be patterned to energetically remove the conductive thin film along this boundary.
    Type: Grant
    Filed: July 20, 1993
    Date of Patent: December 17, 1996
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ciaran Hanrahan, Andrew P. Stack
  • Patent number: 5585599
    Abstract: A housing for electronic devices. The housing has a base having profiled metal bars that have at least one longitudinal chamber, at least one metal covering part that is secured to the base and has an inwardly-chambered strip, and at least one contact spring that has a U-shaped cross-section and is disposed between the metal bars and the covering part. A side wall of the longitudinal chamber is formed by a clamping rib for inserting the contact spring, the chamber having a longitudinal slit which adjoins the clamping rib, and the edge strip of the covering is parallel to the outer side of the clamping rib.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: December 17, 1996
    Inventors: Hans-Martin Schwenk, Henning Wick
  • Patent number: 5586009
    Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: December 17, 1996
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5585998
    Abstract: An isolated sidewall capacitor with dual dielectric, which includes two capacitors. The first capacitor includes a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening. The second capacitor includes the second conductor, a first non-conductor disposed over the top portion of the second conductor, a third conductor disposed over the first non-conductor, and the third conductor electrically connected to the first conductor. A second non-conductor isolates the first conductor from the second conductor.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: December 17, 1996
    Assignee: International Business Machines Corporation
    Inventors: David E. Kotecki, William H. Ma, Katherine L. Saenger
  • Patent number: 5583740
    Abstract: A solid electrolytic capacitor is provided which comprises a capacitor element and a safety fuse. The anode of the capacitor element is electrically connected to an anode lead, whereas the cathode of the capacitor element is electrically connected to a cathode lead through the safety fuse. A resin package encloses the capacitor element, the fuse, a part of the anode lead, and a part of the cathode lead. The resin package has a recess which is formed with a port extending toward the fuse. An elastic closure member is fitted in the recess of the resin package to close the port.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: December 10, 1996
    Assignee: Rohm Co., Ltd.
    Inventor: Shinichi Fujino
  • Patent number: 5583748
    Abstract: A semiconductor module includes a plurality of circuit boards superposed one on another, each circuit board having two opposed surfaces; and groups of electronic parts mounted on the two opposed surfaces of each of the circuit boards, the groups of electronic parts including IC packages, each IC package having a package body and leads extending outward from at least one side surface of the package body, wherein the IC packages mounted between an adjacent pair of the circuit boards in a back-to-back relationship are located on the circuit board so that the leads of one of the IC packages on one of the circuit boards are directly opposite the package body of an IC package on the other of the circuit boards.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: December 10, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hidenobu Gochi, Tetsuro Washida
  • Patent number: 5583739
    Abstract: An on-chip decoupling capacitor is disclosed. The capacitor of the present invention is fabricated using an embedded conductive layered structure. A first insulative layer, a first conductive layer, a second insulative layer, a second conductive layer, and a third insulative layer are deposited sequentially on a substrate having electronic circuitry. Next, a patterning layer is formed to provide for vias for interconnection between metal layers above and below the capacitor plates. An etch is then performed to form a via through the first, second and third insulative layers and the first and second conductive layers. Next, a fourth insulative layer is deposited and anisotropically etched to form sidewall insulators on the vias. Finally, interconnection between lower level metal levels and upper level metal levels is made through the vias. Additionally, methods of coupling the upper and lower capacitor plates to either power or ground are described.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: December 10, 1996
    Assignee: Intel Corporation
    Inventors: Quat T. Vu, Donald S. Gardner