Patents Examined by Bot Ledynh
  • Patent number: 5418692
    Abstract: A tray for semiconductor devices is used by piling up another tray or other trays on this tray. Rectangular pockets are formed on the upper surface of the trays and each of the pockets houses a semiconductor device. A base projects upward from each pocket to support each semiconductor device. The base has a similar shape to and is larger than the undersurface of the semiconductor device. Parallel guide ribs are formed on the undersurface of each tray and each is provided with an tapered inner face inclined downward outward of the base. The roots of the adjacent guide ribs define a portion of the undersurface of the trays which has a similar shape to and is smaller than the upper surface of the semiconductor device. The guide ribs are arranged to provide a horizontal play between the outer edge portions on the upper surface of the semiconductor device and the tapered inner face. An upwardly projecting holding mechanism extends along the outer edge portions.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: May 23, 1995
    Assignee: Shinon Denkisangyo Kabushiki-Kaisha
    Inventor: Hisashi Nemoto
  • Patent number: 5418687
    Abstract: A wafer scale multi-chip semiconductor module used to interconnect and house a plurality of integrated circuit chips. The wafer scale multi-chip semiconductor module has an interconnect network extending between the integrated circuit chips along the substrate of the semiconductor wafer module, which allows electrical access to the integrated circuit chips by means of electrically conductive bridge connections. The integrated circuit chips are placed in openings in the semiconductor wafer module, allowing for excellent planarity.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: May 23, 1995
    Assignee: Hewlett-Packard Company
    Inventor: Yaw-Hwang Chen
  • Patent number: 5418688
    Abstract: An electronic device (100) comprises a first substrate (102) having a first circuit pattern disposed thereon which is selectively processed to provide pretinned connection pads (108, 116, 124, 132, 140) for connection to at least one electronic component (142) and a second circuit pattern disposed on a second substrate (104). The second circuit pattern disposed on the second substrate (104) is selectively processed to further provide pretinned connection pads (110, 118, 126) for connection to the first circuit pattern, and the second substrate (104) further has relief provided within a portion thereof to position the at least one electronic component (142) with respect to the pretinned connection pads (108, 116, 124, 132, 140) on the first circuit pattern.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: May 23, 1995
    Assignee: Motorola, Inc.
    Inventors: Allen D. Hertz, David A. Tribbey, Kenneth Cook, Arthur L. A. Baker
  • Patent number: 5418329
    Abstract: A high frequency IC package includes a dielectric package body having a surface, a high frequency signal transmission line and a power supply line disposed on the surface of the package body, a high frequency IC chip disposed on the surface of the package body and electrically connected to the high frequency signal transmission line and the power supply line by wires, and a lid hermetically sealing and shielding the IC chip. The lid includes a plane part parallel to the surface of the IC chip and side walls, perpendicular to the plane part, surrounding the IC chip. Since the side wall is not present on the surface of the package body but included in the lid, during the wire-bonding process of the IC chip, unfavorable contact between the cavity wall and bonding tool is avoided, reducing the lengths of bonding wires and signal transmission lines. As the result, reflection loss, conductor loss, and cavity resonance are reduced.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: May 23, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takayuki Katoh, Yoshihiro Notani
  • Patent number: 5416668
    Abstract: A shielded member includes a nonconductive housing for mounting on a substrate. The housing includes a cavity and has a base to be received against the substrate. The housing includes at least one integral mounting post extending beyond the base for reception in respective aperture in the substrate. A conductive coating extends over at least a portion of the housing and at least a portion of the integral mounting post. The conductive coating provides shielding for the cavity with currents induced in the conductive coating on the housing conductible to a trace on the substrate by way of the conductive coating on the integral mounting post.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: May 16, 1995
    Assignee: AT&T Corp.
    Inventor: Albert M. Benzoni
  • Patent number: 5414597
    Abstract: An RF shielded electronic module is formed of stamped sheet metal in the form of a wrap having four side walls. A sheet metal cross-member extends between opposed walls and is welded thereto. A printed circuit board is soldered to the cross-member and to the wrap such that the cross-member provides an RF shield between separate areas of components on the printed circuit board. A pair of sheet metal covers are joined to the wrap substantially enclosing the circuit board. The wrap and covers provide an externally shielded enclosure. The wrap, covers, and cross-member provide internal shielded compartments.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: May 9, 1995
    Assignee: Ford Motor Company
    Inventors: Gael D. Lindland, Sylvester P. Porambo
  • Patent number: 5412538
    Abstract: A low-profile printed circuit board has discrete components mounted within openings provided in a rigid substrate forming art of the board. The components are mounted with leads soldered to mounting pads on the surface of the board, and arranged around the periphery of the openings. The stand-off design of discrete components for mounting to the surfaces of boards allows such components to be mounted within openings simply by reversing the orientation of the components relative to the board. In a preferred embodiment a DRAM card is a four-level board with circuitry on each side of a thin, flexible substrate and each side of a rigid substrate, the two substrates spaced apart by a thin, insulating layer. The rigid substrate has openings with DRAM modules mounted within the openings, and further modules are mounted on the opposite surface in the conventional manner.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: May 2, 1995
    Assignee: Cordata, Inc.
    Inventors: Dan Kikinis, William J. Seller
  • Patent number: 5410451
    Abstract: A thin dielectric substrate bearing a plurality of conductive leads has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on a circuit board. The free leads are isolated from pressure applied to the chip on tape assembly after it has been connected to a circuit board by means of a thin self-supporting thermally conductive heat spreader that contacts the side of the die opposite its pads and includes fixed standoff and/or alignment pins that extend through alignment holes in the thin substrate and are in physical contact with a surface of the printed circuit board.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: April 25, 1995
    Assignee: LSI Logic Corporation
    Inventors: Emily Hawthorne, John McCormick
  • Patent number: 5408384
    Abstract: In order to provide a small-sized card and a connector device therefor having no fear of damages and stains of terminals, the card according to the invention has a structure comprising a casing with an opening, and a double-faced substrate on which electronic parts are provided and a plurality of terminals are attached in the vicinity of one end of the substrate, in which the terminals are provided on both the upper and lower surfaces of the substrate, the lower surface of the substrate is disposed in contact with the inner surface of the casing, the terminals on the lower surface of the substrate are covered with a cover which is swung or slid to be opened/closed freely, so that when the card is inserted in a connector device, the cover is opened to expose the lower-surface terminals and to fit them closely in a connector of the connector device.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: April 18, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshimasa Gannyo, Hiroyuki Yamada, Motoyoshi Kitagawa
  • Patent number: 5406028
    Abstract: A packaged semiconductor device has a semiconductor chip and leads formed over the chip with an electrically insulating film interposed therebetween and a packaging material for sealing the chip and the inner lead portions of the leads. The electrically insulating film has such an area as to provide a peripheral portion not covered by parts of the inner lead portions of the leads for strengthening adherence of the electrically insulating film to the packaging material and to the chip. The electrically insulating film has a thickness substantially in a range from 80 .mu.m to 200 .mu.m for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature. A stress absorption film may be formed between the electrically insulating film and the semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature.
    Type: Grant
    Filed: February 18, 1994
    Date of Patent: April 11, 1995
    Assignees: Hitachi, Ltd., Texas Instruments Incorporated
    Inventors: Lim T. Beng, Chai T. Chong, Masazumi Amagai, Ichiro Anjoh, Junichi Arita, Kunihiro Tsubosaki, Masahiro Ichitani, Darvin Edwards
  • Patent number: 5406026
    Abstract: A frame structure for a communication system includes a framework for accommodating a communication system and a cover member mounted on the framework. The cover member has an insulating material layer provided between a semiconducting material layer and a conducting material layer, and is mounted so that the conducting material layer will face inside. The semiconducting material layer and the conducting material layer are electrically connected to each other.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: April 11, 1995
    Assignee: Fujitsu Limited
    Inventors: Akiyoshi Yamaguchi, Yuji Hasegawa, Manabu Miyamoto, Minoru Suzuki, Koichi Abe, Hideki Sonobe, Sadayuki Tetsu
  • Patent number: 5406455
    Abstract: A holder for holding polygonal shaped objects (i.e., printed circuit boards) and adapted to be slidably engaged with a rigid U-shaped enclosure, includes first and second integrally-formed frames and a mechanism for locking the frames into the U-shaped enclosure. The locking mechanism is integrally formed with the frames. A device mounted on the frames receives and holds the rectangular objects. The holder is easily inserted into and removed from the enclosure, allows efficient assembly and disassembly of the holder into and from the enclosure, and reduces the required number of pans and assembly/disassembly time in comparison to conventional holders.
    Type: Grant
    Filed: August 16, 1993
    Date of Patent: April 11, 1995
    Assignee: NEC America, Inc.
    Inventor: William R. Devenish, III
  • Patent number: 5406027
    Abstract: The present invention relates to a mounting structure adapted to be mainly used commercially and to an electronic device employing such mounting structure. A board carrying a plurality of chips is directly coated with resin to form a casing or a part thereof. Alternatively a plurality of the boards interconnected by flexible wiring sheets and coated with resin with retaining the flexibility of the wiring sheets. Such structure helps to provide a handy electric device which is required to be compact, light-weight and thin.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: April 11, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kunio Matsumoto, Kazuo Hirota, Munehisa Kishimoto
  • Patent number: 5403975
    Abstract: A process for producing electronic package components from an aluminum alloy is disclosed. The components have a black color through integral color anodization. The desired color, thickness and surface finish are achieved by regulation of amperage during anodization. The amperage is rapidly raised to in excess of 80 amps per square foot and then allowed to gradually decrease as a function of oxide growth.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: April 4, 1995
    Assignee: Olin Corporation
    Inventors: Anthony M. Pasqualoni, Deepak Mahulikar, Satish K. Jalota, Andrew J. Brock
  • Patent number: 5404273
    Abstract: A semiconductor-device package includes: a printed circuit board which has a chip-accommodating hole in its center portion and which has external connection terminals formed on its one side and a flexible substrate which has a supporting film having a central hole coaxial with the chip-accommodating hole, a given circuit pattern which is formed on the supporting film and inner leads which project inside the central hole and which have micro patterns, the flexible substrate being bonded on the other side of the circuit pattern of the printed circuit board with electrical conduction between them.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: April 4, 1995
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Masatoshi Akagawa
  • Patent number: 5400949
    Abstract: A circuit board assembly including a shielding housing mounted on a circuit board (1), the shielding housing being intended for radio-frequency shieldings. The shielding housing (2) having a wall inclined at an angle .alpha. to a plane orthogonal to the plane of the circuit board. The housing of the circuit board assembly being suitable for at least a partial embedding into an exterior wall of an electronic apparatus.
    Type: Grant
    Filed: January 18, 1994
    Date of Patent: March 28, 1995
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Timo Hirvonen, Ari Leman, Veli-Matti Valimaa, Petri Hossi, Jari Olkkola, Lasse Uronen
  • Patent number: 5402315
    Abstract: An assembly module for a printed circuit board for the connection of screened conductors includes a metallic grounding plate comprising multiple modules. Each module includes a mechanism for fixedly connecting the module to a printed circuit board and at least one spring clamp conductively supported on the module. The clamp has an approximately shell-shaped conductor accommodating area for detachably enclosing at least one screened conductor. The plate further includes one rated breakage point between each two adjacent modules so that adjacent modules may be separated from one another by breaking the plate at the rated breakage point.
    Type: Grant
    Filed: July 20, 1993
    Date of Patent: March 28, 1995
    Assignee: Reichle+De-Massari AG
    Inventor: Hans Reichle
  • Patent number: 5401901
    Abstract: Weather-resistant electromagnetic radiation shielding materials and structures for electromagnetic interference attenuation for electronic equipment situated in unshielded outdoor housings are described.
    Type: Grant
    Filed: September 19, 1991
    Date of Patent: March 28, 1995
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Michael Gerry, David Z. Kelly, Michael G. Ryan, Thomas E. Dykes, Robert Sassa
  • Patent number: 5402322
    Abstract: A wall-mounted enclosure for mounting electrical and electronic equipment and the like, in modular form. The enclosure body takes the form of a mounting assembly, including mounting modules, with each module including a backbone element and a cover element. The backbone element has a horizontally extending backplane bordered by two upstanding side portions, with an interassembly connecting mechanism for joining one backbone element to an adjacent backbone element. The backplane includes a flat mounting surface, with a pattern of preformed pilot holes, and two recessed wiring channels. Interconnection is provided by interlocks and screw anchor points. The cover element includes a horizontally extending cover plate with coverwalls and a cover assembly connecting mechanism for joining one cover element to another cover element. Adjacent cover elements are joined by mutual engagement of a mating tab and slot, and by screw anchor points.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: March 28, 1995
    Assignee: Johnson Service Company
    Inventors: Jeffery S. Kunkler, Gene D. Goetz
  • Patent number: 5402323
    Abstract: An equipment cabinet for insertable electrical and electronic units includes stationary casing components and a door pivotally attached by means of hinges. The door and the end faces of the casing components disposed opposite thereto are each provided with peripheral edge strips which are bent inwardly at an acute angle of preferably 45.degree. and have parallel sealing faces that face one another at a slight distance. Between the sealing faces, spring-elastic seals are provided that may be composed of contact strips of an electrically well conducting material and rubber-elastic sealing strips arranged parallel thereto. Due to the sloped arrangement of the sealing faces, the spring forces F exerted by the seals are divided into two force components F.sub.1 and F.sub.2, with only the one force component F.sub.1 having to be overcome when the door is pushed shut.
    Type: Grant
    Filed: August 19, 1992
    Date of Patent: March 28, 1995
    Assignee: Schroff GmbH
    Inventors: Hans M. Schwenk, Kurt Pohl, Gerhard Huller