Abstract: Embodiments of the present disclosure include techniques for transferring non-power of two (2) bytes of data between modules of an integrated circuit over an on-chip communication fabric. In one embodiment, the present disclosure includes an on-chip communication fabric, a first module comprising an interface coupled to the fabric having a first data width, and a second module comprising an interface coupled to the fabric having a second data width smaller than the first data width. The non-power of two (2) bytes of data are sent between the first and second modules through the fabric, and the fabric maps the non-power of two (2) bytes of data between the first and second data widths.

Abstract: A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

Abstract: A data processing system includes a host and an accelerator. The host transmits, to the accelerator, input data together with data identification information based on a data classification criterion. The accelerator classifies the input data as any one of feature data, a parameter, and a bias based on the data identification information when the input data is received from the host, distributes the input data, performs pre-processing on the feature data, and outputs computed result data to the host or feeds the result data back so that computation processing is performed on the result data again.

Abstract: A method for communicating between a master and a plurality of slaves includes generating a communication frame including generating a slave data frame in each slave. The slave data frame has a data packet including one or more data bytes and at least one gap of variable time length comprising no information in the slave data frame. The gap may be at the beginning of said slave data frame before the beginning of the first data byte of said data packet and/or at the end of said data packet after the end of a last data byte of said data packet, where the gaps have a time length dependency based on parameters locally stored in each of said at least one slave. The slave data frame is transmitted sequentially where the gap increases for each subsequent slave.

Abstract: An indication that a virtual machine is starting is received. Requested data blocks associated with the virtual machine are identified. Based on identifiers of the requested data blocks, a trained learning model is used to predict one or more subsequent data blocks likely to be requested while the virtual machine is starting. The one or more subsequent data blocks are caused to be preloaded in a cache storage.

Abstract: A device for a serial bus system. The device has a receiver receiving a signal from a bus of the bus system. For a message exchanged between user stations of the bus system, a recessive bus state is overwritable by a dominant bus state and the recessive bus state is generated differently in the first communication phase than in the second communication phase. The receiver generates a digital signal based on the received signal, and the signal being output to a communication control unit for evaluating the data contained in the digital signal. The receiver uses a first and second reception threshold for generating the digital signal in the second communication phase, the second reception threshold having a voltage value lower than that of the first reception threshold or higher than the highest voltage value which, during normal operation, is established on the bus for a dominant bus.

Abstract: Technologies for improving enumeration of universal serial bus (USB) devices over a media agnostic USB (MAUSB) connection are disclosed. In the illustrative embodiment, an MAUSB device may send USB configuration data to a host compute device. The host compute device may then perform a virtual enumeration of the USB devices based on the USB configuration data without necessarily communicating with the USB devices. The MAUSB device may perform an enumeration of the USB devices on behalf of the host compute devices without necessarily communicating with the host compute device. The USB devices may not be aware or have any indication that the USB device is not communicating with the host compute device during the enumeration process. Such an approach may improve the latency of USB enumeration over an MAUSB connection.

Abstract: The present disclosure includes a system including a power supply unit that provides an output power and a supply status indicating whether the power supply unit is receiving input power. An electronic circuit is coupled to the power supply unit to receive the output power and a standby control circuit controls turning on and off the power supply unit. A power harvesting circuit generates standby power from the supply status and provides the standby power to power the standby control circuit.

Abstract: In some examples, an adapter device includes a bridge to determine that a storage device includes a plurality of bus controllers, where the plurality of bus controllers are communicatively coupled to respective adapter devices. The bridge determines a quantity of supported connections over the network to the storage device, and in response to determining that the storage device comprises the plurality of bus controllers, the bridge computes an identifier based on the quantity of supported connections and to which respective bus controller of the plurality of bus controllers the adapter device is connected, and assigns the identifier to a connection from the host to the storage device.

Abstract: A data processing apparatus includes a master device configured to transmit commands for destinations, a slave device including a plurality of command processing regions respectively corresponding to the destinations, and a controller configured to relay communication between the master device and the slave device. The controller assigns time stamp value to the commands as an initial value when the commands was received by the controller and increment the time stamp value every command arbitration cycle, selects a command having a largest time stamp value among the commands in a tournament manner by comparing commands having different destinations every command arbitration cycle, stores a command selection history of each comparison of commands, selects the command based on a command selection history corresponding to the compared commands when respective time stamp values of the compared commands are the same or substantially the same as each other.

Abstract: A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a set-reset latch circuit receiving a normal access request signal and a refresh access request signal as first and second input signals and generating a first output signal having zero or more signal transitions in response to the order the first input signal and the second input signal is asserted. The arbitration control circuit further includes a unidirectional delay circuit applying a unidirectional delay to the first output signal and a D-flip-flop circuit latching the first output signal as data in response to the delayed signal as clock. The D-flip-flop generates a second output signal having a first logical state indicative of granting the normal access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.

Abstract: A system, method, and computer-readable medium are disclosed for securing hot-pluggable ports, such as USB ports, of an information handling system, by isolating a dedicated controller from the operating system of the information handling system. Devices that are to be allowed to be enabled at the ports are determined. A hash signature is created and saved to verify the devices. The controller and ports are held in reset until the devices are authenticated.

Abstract: An electronic device includes a transmit buffer, a receive buffer, a communication port, and a controller. The controller is to: communicate with a target device via a data link established via the communication port; determine a throughput ratio between the transmit buffer and the receive buffer; in response to a determination that the throughput ratio is above a threshold, transmit a request to the target device to change an aspect of the data link, where the request includes a payload size indicating an amount of data to be transmitted from the electronic device to the target device; and in response to receiving a grant message associated with the request, increase an amount of transmit lanes within the data link from the electronic device to the target device.

Abstract: An information handling system includes a compression client, a memory, and a SDXI hardware module. The compression client issues a compression request for a block of data that is uncompressed. The memory has multiple storage locations identified by addresses, which include a source address and a destination address. The SDXI hardware module performs compression of the block of data to create compressed data of the block of data. The SDXI hardware module determines whether an amount of the compression of the block of data is less than a threshold amount of compression. In response to the amount of the compression being less than the threshold amount of compression, the SDXI hardware module disregards the compressed data of the block of data, and utilizes the uncompressed block of data in a source address. The SDXI hardware module updates metadata for the block of data to indicate that data returned to compression client is uncompressed.

Abstract: Techniques are disclosed relating to a method that includes monitoring, by a sideband processor, a plurality of operating conditions of a computer system using a first set of commands. This first set of commands are sent utilizing a particular command protocol over a particular communication bus. In addition, the sideband processor may be modified to support a second set of commands. The sideband processor may receive data for a particular device in the computer system. The sideband processor may modify a first command of the first set of commands to include a second command of the second set of commands. This second command may include an address associated with the particular device and at least a portion of the data. The sideband processor may then send the modified first command to a controller hub using the particular command protocol over the particular communication bus.

Abstract: Example of systems with rotatable port units are described. In an example, a system includes a control unit, a first port unit with a first set of ports coupled to the control unit, and a second port unit with a second set of ports coupled to the control unit. The second port unit is mounted on the first port unit and is rotatable with respect to the first port unit. The control unit is to enable a sub-set of ports from the second set of ports and the first set of ports based on a rotational position of the second port unit with respect to the first port unit.

Abstract: An electronic device may include a connection unit including four ports for connecting an external audio device; a codec configured to generate an audio signal transmitted to the external audio device; a first switch unit configured to, if the external audio device is electrically connected to the electronic device, connect the first port and the second port with the codec; a second switch unit configured to, if the external audio device is electrically connected to the electronic device, connect the third port and the fourth port with the codec; a third switch unit configured to swap connection directions of the third port and the fourth port according to a coupling orientation of the external audio device and the electronic device; and a ground unit connected to the third port and the fourth port and configured to ground one of the third port and the fourth port.

Abstract: A centralized access control circuit includes a memory, a sub-circuit, and a memory controller. The memory includes a plurality of lock bits mapped to a plurality of bytes of a peripheral register included in a peripheral. The sub-circuit receives, from a processor core, an access request to access a set of bytes of the plurality of bytes. The sub-circuit grants a first level of access privilege to the processor core based on an identifier of the processor core and an address of the set of bytes included in the access request. The memory controller receives the access request and grants, based on a value of each of a set of lock bits mapped to the set of bytes, a second level of access privilege to the processor core. The processor core accesses the set of bytes based on the first and second levels of access privileges.