Abstract: Provided are a parallel processing system and an operation method thereof. The parallel processing system includes: a bus; a plurality of parallel processing processors; a plurality of shared memories connected to the bus via separate individual channels and connected to each other via a memory connection line; and a main processor configured to set a broadcasting state for the plurality of shared memories and control data stored in one shared memory among the plurality of shared memories to be broadcast to another shared memory via the memory connection line according to the broadcasting state.

Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.

Abstract: In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.

Abstract: Provided is a communication apparatus including: a first communication portion configured to perform wireless communications with an external apparatus based on a Bluetooth Low Energy communication scheme; and a first determiner configured to determine whether an auto power-on function of powering on the communication apparatus under a predetermined condition even when the communication apparatus is in a powered-off state is set to be enabled, wherein, when the first determiner determines that the auto power-on function is set to be enabled, the first communication portion disconnects connection to the external apparatus, which has been established based on the Bluetooth Low Energy communication scheme, in response to a power-off instruction, and transmits advertising information that allows a response based on the Bluetooth Low Energy communication scheme to be received.

Abstract: In one embodiment, an electronic device controls an external conversion device connected to an external device. The electronic device includes a connection terminal formed on a portion of an outer surface thereof, a first converter connected to the connection terminal and configured to convert signals, and a processor operatively connected to the first converter. The processor is configured, when the external conversion device is connected to the connection terminal, and the external device is connected to the external conversion device, to identify a type of the external device connected to the external conversion device by receiving an operation signal of the external device through the external conversion device, the connection terminal, and the first converter, and to input or output a signal corresponding to the external device through the external conversion device.

Abstract: A memory card includes a card substrate on which a controller and a memory device are mounted, and a card enclosure that accommodates the card substrate and exposes terminals for electrical connection to an external device. The controller is operable in a universal flash storage (UFS) mode and in a first sub-mode other than the UFS mode. The terminals that are exposed include a UFS terminal group according to a UFS standard, and a first sub-mode terminal group. The UFS terminal group includes first row terminals arranged adjacent to an insertion side edge of the memory card and second row terminals arranged apart from the insertion side edge such that the first row terminals are provided between the second row terminals and the insertion side edge. The first sub-mode terminal group is adjacent to the first row terminals.

Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Abstract: A communication system including a physical layer circuit, a timer circuit, and a turnaround controller. The physical layer circuit provides an early turnaround indication upon detection of a turnaround command and before completion of the turnaround command. The timer circuit is programmed with a timeout value indicative of a maximum time of a turnaround procedure initiated by the turnaround command. The turnaround controller starts the timer circuit in response to the early turnaround indication. A transmit controller may begin retrieving information to transmit from a memory in response to the early turnaround indication, and may begin transmitting the retrieved information if the turnaround procedure completes before timeout of the timer circuit. The retrieved information may be configuration information for a sensor. The turnaround controller provides an error indication if the timer circuit times out indicating a turnaround error. The error indication enables remedial action to be taken.

Abstract: A method includes detecting, by a first LVDC affiliated with a first host device, a request for a one-to-one communication with a second LVDC affiliated with a second host device, where data is conveyed between the LVDCs by varying loading on a bus at a frequency. The method further includes determining a desired number of channels to support the one-to-one communication based on one or more of: the first host device, the second host device, and information contained in the request, wherein the channels correspond to frequencies in a frequency band. The method further includes determining whether the desired number of channels is available for the one-to-one communication. When the desired number of channels is available for the one-to-one communication, allocating them for the one-to-one communication.

Abstract: A host device comprises a processor coupled to a memory. The host device is configured to obtain from a storage system connectivity information characterizing one or more ports of the storage system, and to automatically establish connectivity of a particular type between the host device and one or more logical storage devices of the storage system based at least in part on the obtained connectivity information. For example, the host device can obtain the connectivity information directly from the storage system or via at least one intermediary device such as a management station. In some embodiments, the obtaining and automatically establishing are performed by at least one multi-path input-output driver of a multi-path layer of the host device. The connectivity of a particular type illustratively comprises Internet Small Computer System Interface (iSCSI) connectivity between the host device and the storage system, although other connectivity types can be supported.

Abstract: An electronic device according to various embodiments includes: a connector configured to be connected with an external electronic device; a memory configured to store instructions; and a processor configured to execute the stored instructions to control the electronic device to identify a control signal received through a channel initially activated based on the external electronic device being connected to the connector from among a plurality of channels, and to perform control based on a message included in the identified control signal.

Abstract: Systems, methods, and computer-readable media are disclosed for mitigating thermal increases in electronic devices. Example devices may include memory and at least one processor configured to access the memory and execute computer-executable instructions to determine that a temperature of the device satisfies a first threshold, send a notification to an access point communicatively coupled to the device indicating that the device will enter a sleep state for a length of time, and cause the device to enter the sleep state. Certain embodiments may be configured to cause the device to enter an awake state after the length of time, determine that the temperature satisfies a second threshold, and determine that a period of time has elapsed. Some embodiments may be configured to determine that a first bandwidth mode is active at the device, and cause a second bandwidth mode to be activated at the device.

Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

Abstract: A controller for providing a DRP port according to USB Type-C standard. A state manager coupled to a power manager for controlling charging and discharging of a battery. A signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable according to an instruction from the state manager. The signal transmission module is possible to indicate the communication line whether the port is featured as the power supply side or the power reception side. When the port is featured as the power supply side, the state manager supplies an electric power stored in the battery to the connection destination and if the battery becomes the condition of Low Battery, the state manager stops supplying the electric power to the connection destination while maintaining the state that the port is featured as the power supply side.

Abstract: An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.

Abstract: An information handling system includes a device, a processor, and a runtime agent. the device provides a System Management Interrupt (SMI) in response to an error on the device. The processor receives the SMI, enters a System Management Mode (SMM), and executes first interrupt handler code in SMM to provide interrupt information associated with the SMI when the SMI is associated with a non-critical error on the device, and exit SMM to a runtime mode. The runtime agent receives the interrupt information during the runtime mode to execute second interrupt handler code to service the non-critical error on the device.

Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

Abstract: Methods, apparatus, and computer-readable media are described to encode, by a first station (STA), a polling signal for periodic transmission to a second STA during each air activity instance of a plurality of air activity instances. The first STA detects an interface between a MAC layer and a software stack of a communication protocol is in a low-power state. The communication protocol is associated with a communication link between the first STA and the second STA. An empty packet from the second STA is decoded. The empty packet is received in response to the polling signal transmitted during an air activity instance of the plurality of air activity instances. The periodicity of the periodic transmission of the polling signal is adjusted based on the detected low-power state and the decoded empty packet.

Abstract: A convertible I/O signal processor is convertible between different operating configurations for connecting multiple field devices to the I/O signal processor by selectable types of electrical connectors such as cables, terminal blocks, and the like. The I/O signal processor includes a signal processing module connected to a signal processor and an interface module removably connected to the signal processing module. The interface module includes electrical connectors for receiving/transmitting I/O signals from and to field devices. The interface module and the signal processing module define I/O channels extending between the electrical connectors and the signal processor. The interface module in embodiments includes I/O module connectors that enable removable I/O modules to be interposed in the I/O channels.

Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.