Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.

Abstract: Method for controlling commands suitable to be processed by a peripheral (2) comprising the following steps implemented by a control circuit (6) connected to a communication bus (8), a command circuit (4) and the peripheral (3) also being connected to the communication bus (8): granting or refusing authorization to the command circuit (4) to transmit a command signal of the peripheral via the bus (8), detecting the possible transmission of the command signal for the peripheral by the command circuit via the bus (8), implementing protection measures (614) when the control circuit detects that the command signal has been transmitted as the control circuit has not granted authorization, or that the command signal has not been transmitted as the control circuit has granted authorization.

Abstract: A method may include initializing operation of a baseboard management controller at an information handling system. The baseboard management controller includes a real time clock. The method further includes receiving clock information from a real time clock circuit included at a field programmable gate array. The clock information at the real time clock at the baseboard management controller can be updated with the clock information received from the real time clock circuit included at the field programmable gate array.

Abstract: A system, computer-readable media and computer-implemented method for automated network adapter activation in connection with fibre channel uplink mapping. The system includes a non-virtualized storage area network switch having a plurality of fibre channel ports. Each of the fibre channel ports is coupled to a corresponding cable to at least partly define a fibre channel uplink. The system also includes a plurality of client devices. Each client device has a network adapter.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit (DAC), a receive analog DAC and a drive sense circuit configured to receive transmit digital data. The transmit DAC is configured to convert transmit digital data into an analog outbound data signal and the receive analog DAC is configured to convert an analog outbound data signal into an analog transmit signal. The drive sense circuit is configured to drive the analog transmit signal on to a bus coupled to the low voltage drive circuit as a signal that varies loading on the bus at a first frequency to represent the analog outbound data signal. The drive sense circuit is further configured to receive an analog receive signal from the bus at a second frequency, convert the analog receive signal into an analog inbound data signal, convert the analog inbound data signal into received digital data, and output the received digital data.

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The memory system can include a pipeline for accessing data stored in one of the caches. Requestors can access the data stored in one of the caches by sending requests at a same time that can be arbitrated by the pipeline.

Abstract: A method of transferring data from a first bus to a second bus across an asynchronous interface using an asynchronous bridge. The bridge comprises a bus slave module, connected to the first bus, comprising a forward-channel initiator in a first power and/or clock domain; and a bus master module, connected to the second bus, comprising a forward-channel terminator in a second power and/or clock domain. The forward-channel initiator and terminator are in communication to form a forward lockable mutex for arbitrating access to signals used to transfer data from the first domain to the second domain. If the mutex is locked, a forward data channel is used to transfer data between the domains. Otherwise if the mutex is unlocked, the forward channel initiator toggles a status request signal and the forward channel terminator toggles a status acknowledge signal in response, the mutex thereby becoming locked.

Abstract: A system for automatically addressing serially connected slave devices includes a master device and multiple slave devices each including a serial communication transceiver, an address input port, an address output port, and a controller. The system also includes a serial communication wiring bus connected between the serial communication transceivers of the master and slave devices, and at least one digital address line connected between the address input ports and the address output ports. Each controller is configured to receive a PWM or PFM signal from a previous one of the multiple slave devices, determine an address for the slave device including the controller according to the received PWM or PFM signal, and transmit a PWM or PFM signal indicative of the determined address to a subsequent one of the multiple slave devices.

Abstract: The signal collection method is a method that collects internal states indicated by signals in an electronic circuit device including a bus, the signal collection method including: storing the internal states with a fine resolution data storage by obtaining the internal states per a first period; per a second period, which is longer than the first period: obtaining a first data transfer amount, which is a data amount transferred by the bus, via a coarse resolution data storage; calculating a difference between a second data transfer amount and the first data transfer amount obtained in the obtaining, the second data transfer amount being calculated in advance and obtained from a cycle pattern generator; and determining whether the difference calculated in the calculating is within a predetermined range to stop storing in the storing when it is determined that the difference is not within the predetermined range.

Abstract: A slave device includes an SPI bus with a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device. The slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device.

Abstract: A bi-directional signal transmission connection cable is disclosed. The bi-directional signal transmission connection cable can be connected between a first and a second electronic device. The bi-directional signal transmission connection cable includes a first connection port, a second connection port, a first repeater chip, a second repeater chip and a plurality of transmission wires. The first and the second repeater chips are symmetrically disposed in the first and the second connection ports. The first repeater chip has a first set of adjustment parameters, and the second repeater chip has a second set of adjustment parameters. Thus, when a signal is transmitted between the first and the second electronic devices via the first connection port, the second connection port, and the plurality of transmission wires, the signal is adjusted by the first set of adjustment parameters and the second set of adjustment parameters.

Abstract: A method for executing device management commands includes providing a device management command queue indication. The method also includes receiving, from a host in response to providing the device management command queue indication, device management commands and a respective command type for each device management command. The method also includes determining a command execution order for the device management commands based on the command types corresponding to respective device management commands and queueing, in a device management command queue, the device management commands based on the command execution order. The method also includes executing the device management commands according to the device management command queue. The method also includes communicating, to the host, a command execution indication responsive to executing the device management commands.

Abstract: A chip processing device and a method for chip processing using the same is provided, where the device can program, detect, reset or inspect a plurality of chips, and meanwhile has one or more functions of programming, detecting, identifying, resetting or inspecting. The plurality of chips has different communication interfaces, and/or uses different communication protocols. The chip processing device can be configured to program, detect, identify, reset or inspect a chip after obtaining the model of the chip to be processed, thus having higher universality.

Abstract: A sniffer bus-based network General Purpose Interface Bus (GPIB) module includes two functional units. One is Data Acquisition Unit (DAU) module, and the other one is Data Processing Unit (DPU) module. The DPU is configured to receive data from the (DAU) module and converting the data by time-stamping and a host server configured to receive JSON format data via a communication network. Further, captured data is transferred to the cloud for big data analysis to obtain the specifics of equipment utilization and evaluate the overall efficiency of the test system.

Abstract: Systems and methods enable data collection and analytics consumption with a generalized assurance framework using a message bus that supports a publish-subscribe model. A producer network element subscribes to a request topic on the message bus and posts, to the message bus, an announcement indicating a data topic is available from the producer network element. The producer network element receives via the message bus, the request topic including a request for the data topic and posts, to the message bus, records for the data topic in response to the request.

Abstract: Disclosed are an acceleration control system based on a binarization algorithm, a chip, and a robot, which is configured to read and write an external image memory by means of an AHB bus. The acceleration control system includes a main control module, a binarization module, and a binarization FIFO module, and the main control module is configured to control the AHB bus to read pixel data to be processed in the image memory and control current pixel data in the AHB bus to be burst-transmitted to the binarization module for processing when a main state machine is in a burst read mode state, and meanwhile control the binarization FIFO module to read binarized data obtained and when all of the pixel data stored in the image memory is processed, and it is notified to send an interrupt instruction to a CPU.

Abstract: A hardware serial adapter that can be connected to a serial port of a physical computing device and is associated with network credentials that include a unique hardware identifier and other security information. Upon receipt of data (or other initiation command), the hardware serial adapter transmits a registration request with the network credentials to a distributed network service. If the network credentials are valid, the network service provides communication channel configuration information and session credentials to establish a secure communication for the transmission of data from the hardware serial adapter to a virtual machine instance. The distributed network service can control and manage data transmissions and the communication channel.

Abstract: A method and system for realizing synchronous display of LED light strings based on a high-precision clock signal, which relates to the field of LED technology and specifically comprises the steps of: performing synchronization timing for a data processing module based on a high-precision clock signal to generate a standard clock; dividing the standard clock into several time periods, each time period circularly corresponding to a group of program data; and converting the program data into a suitable control signal by means of a data conversion module and outputting it to the LED light strings. The present invention enables LED light strings of different controllers to change synchronously, and the distances between the controllers are not limited, and the synchronization effect can be achieved whenever the power is turned on.

Abstract: A system may include a first device and a second device communicatively coupled to the first device via a communications bus, wherein the communications bus comprises a single clock line for transmission of a clock signal from the first device to the second device, a single frame line for transmission of a frame alignment signal from the first device to the second device, and at least one communications channel for serialized communication of payloads of data between the first device and the second device, wherein the payloads of data have at least two different latencies.

Abstract: A first medical device can receive a physiological parameter value from a second medical device. The second physiological parameter value may be formatted according to a protocol not used by the first medical device such that the first medical device is not able to process the second physiological parameter value to produce a displayable output value. The first medical device can pass the physiological parameter data from the first medical device to a separate translation module and receive translated parameter data from the translation module at the first medical device. The translated parameter data can be processed for display by the first medical device. The first medical device can output a value from the translated parameter data for display on the first medical device or an auxiliary device.