Abstract: An array substrate provided comprises a gate insulating layer, touch control element and first conducting wire disposed on a substrate; insulating interlayer covering gate insulating layer, touch control element and first conducting wire; protective wire arranged along the surface periphery of insulating interlayer; planarization layer covering insulating interlayer and protective wire, and second conducting wire disposed on surface of planarization layer; wherein touch control element is insulated from first conducting wire comprising an extension section, and free end of extension section is a first end; protective wire is electrically connected with first end; second conducting wire comprises a second and third end arranged oppositely and a contact position between second and third end; second end is electrically connected with touch control element, and contact position is electrically connected with a portion of first conducting wire inner substrate.

Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.

Abstract: A biosensor with a heater embedded therein is provided. A semiconductor substrate comprises a source region and a drain region. The heater is under the semiconductor substrate. A sensing well is over the semiconductor substrate, laterally between the source region and the drain region. A sensing layer lines the sensing well. A method for manufacturing the biosensor is also provided.

Abstract: A wiring substrate includes a substrate body, a post formed on an upper surface of the substrate body, a thin film capacitor, and a first insulation layer covering the thin film capacitor and the post. The thin film capacitor includes a reference hole extending through the thin film capacitor in a thickness-wise direction. The post is inserted through the reference hole.

Abstract: A semiconductor device includes: a p type first semiconductor layer that contains acceptors as impurities; an n type second semiconductor layer that is provided on the first semiconductor layer and contains donors as impurities; and a p type first diffusion portion that includes a contact portion in contact with the first semiconductor layer, the contact portion containing acceptors whose concentration is higher than that in the first semiconductor layer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.

Abstract: A resistive memory device includes a first electrode, a second electrode spaced from the first electrode along a spacing direction, and a hafnium oxide resistive material portion of a resistive memory cell located between the first electrode and the second electrode and having a compositional modulation in oxygen concentration within directions that are perpendicular to the spacing direction.

Abstract: A semiconductor device includes a first conductive wiring, at least one first dielectric layer, at least one second dielectric layer and a second conductive wiring. The at least one first dielectric layer is over the first conductive wiring. The at least one second dielectric layer is over the at least one first dielectric layer. The second conductive wiring is over the at least one second dielectric layer. The dielectric constant of the at least one second dielectric layer is higher than the dielectric constant of the at least one first dielectric layer.

Abstract: A method of providing an out-of-plane semiconductor structure and a structure fabricated thereby is disclosed. The method comprises acts of: providing a substrate defining a major surface; providing a template layer having a predetermined template thickness on the major surface of the substrate; forming a recess in the template layer having a recess pattern and a recess depth smaller than the template thickness; and epitaxilally growing a semiconductor structure from the recess. A planar shape of the recess pattern formed in the template layer substantially dictates an extending direction of the semiconductor structure.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.

Abstract: A system and method to evaluate building heating fuel consumption with the aid of a digital computer is described. The evaluation can be used for quantifying personalized electric and fuel bill savings. Such savings may be associated with investment decisions relating to building envelope improvements; HVAC equipment improvements; delivery system efficiency improvements; and fuel switching. The results can also be used for assessing the cost/benefit of behavioral changes, such as changing thermostat temperature settings. Similarly, the results can be used for optimizing an HVAC control system algorithm based on current and forecasted outdoor temperature and on current and forecasted solar irradiance to satisfy consumer preferences in a least cost manner. Finally, the results can be used to correctly size a photovoltaic (PV) system to satisfy needs prior to investments by anticipating existing energy usage and the associated change in usage based on planned investments.

Abstract: A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

Abstract: A method for producing an electrical device including an electrical component at least partially covered by a covering material having a cement material includes supplying the cement material, mixing an additive into the cement material, applying the covering material having the cement material with the additive onto the electrical component, and treating the covering material. The treatment allows the additive from the cement material to reach a surface of the cement material and to form a protective layer on the surface.

Abstract: A semiconductor device having an EMI shield layer and/or EMI shielding wires, and a manufacturing method thereof, are provided. In an example embodiment, the semiconductor device includes a semiconductor die, an EMI shield layer shielding the semiconductor die, and an encapsulating portion encapsulating the EMI shield layer. In another example embodiment, the semiconductor device further includes EMI shielding wires extending from the EMI shield layer and shielding the semiconductor die.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer. The method further includes (a) depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer and (b) depositing a third encapsulation layer: (i) on the second encapsulation layer which is on the first encapsulation layer and the exposed surface of the dielectric layer. The method also includes etching the remaining layers of the stack/structure (via one or more etch processes).

Abstract: A transistor device includes a first emitter region of a first doping type, a second emitter region of a second doping type, a body of the second doping type, a drift region of the first doping type, a field-stop region of the first doping type, at least one boost structure, and a gate electrode. The boost structure is arranged between the field-stop region and the second emitter region. The at least one boost structure includes a base region of the first doping type and at least one auxiliary emitter region of the second doping type separated from the second emitter region by the base region. An overall dopant dose in the drift region and the field-stop region in a current flow direction of the transistor device is higher than a breakthrough charge of a semiconductor material of the drift region and the field-stop region.

Abstract: A ceramic layer is attached to a top surface of a base plate using a bond layer. The ceramic layer has a top surface configured to support a substrate. At least one clamp electrode is positioned within an upper region of the ceramic layer. A primary radiofrequency (RF) power delivery electrode is positioned within the ceramic layer at a location vertically below the at least one clamp electrode such that a region of the ceramic layer between the primary RF power delivery electrode and the at least one clamp electrode is substantially free of other electrically conductive material. A plurality of RF power delivery connection modules is distributed in a substantially uniform manner about a perimeter of the ceramic layer. Each of the RF power delivery connection modules is configured to form an electrical connection from the base plate to the primary RF power delivery electrode at its respective location.

Abstract: According to one embodiment, a magnetic device comprising a magnetoresistive effect element, wherein the magnetoresistive effect element includes: a first ferromagnetic body, a second ferromagnetic body, and a first rare-earth ferromagnetic oxide that is provided between the first ferromagnetic body and the second ferromagnetic body and magnetically joins the first ferromagnetic body and the second ferromagnetic body.