Abstract: A method of encapsulating a thin-film based thermoelectric module includes forming the thin-film based thermoelectric module by sputter depositing pairs of N-type thermoelectric legs and P-type thermoelectric legs electrically in contact with one another on a flexible substrate having a dimensional thickness less than or equal to 25 ?m, and rendering the formed thin-film based thermoelectric module flexible and less than or equal to 100 ?m in dimensional thickness based on choices of fabrication processes with respect to layers of the formed thin-film based thermoelectric module. The method also includes encapsulating the formed thin-film based thermoelectric module with an elastomer to render the flexibility thereto. The elastomer encapsulation has a dimensional thickness less than or equal to 15 ?m, and the flexibility enables an array of thin-film based thermoelectric modules to be completely wrappable and bendable around a system element from which the array is configured to derive thermoelectric power.

Abstract: A semiconductor component and an illumination device is disclosed. In an embodiment the semiconductor component includes a semiconductor chip configured to generate a primary radiation having a first peak wavelength and a radiation conversion element arranged on the semiconductor chip. The radiation conversion element includes a quantum structure that converts the primary radiation at least partly into secondary radiation having a second peak wavelength and a substrate that is transmissive to the primary radiation.

Abstract: An operating method of a processing liquid supply apparatus which supplies a processing liquid to a substrate from a processing liquid supply path via a nozzle includes measuring a surface potential of a first electrode which is configured to be in contact with the processing liquid of the processing liquid supply path. The operating method further includes displaying the measured surface potential in the measuring of the surface potential of the first electrode.

Abstract: Provided is an active matrix substrate that includes a substrate, a thin film transistor, an electrode layer, and a second insulating film. The thin film transistor is provided on the substrate and includes an oxide semiconductor layer, a gate electrode, and source and drain electrodes. The oxide semiconductor layer includes a first region as a channel region. The electrode layer is level with the gate electrode, is provided in a different region from the thin film transistor, and includes a first end. The second insulating film is provided between the substrate and the electrode layer and includes a second end at a more retreated position than the first end of the electrode layer. The oxide semiconductor layer further includes a second region having lower resistance than the first region. The electrode layer is electrically coupled, at the first end, to the second region of the oxide semiconductor layer.

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

Abstract: A semiconductor device includes a first SiGe fin formed on a substrate and including a first amount of Ge, and a second SiGe fin formed on a substrate and including a central portion including a second amount of Ge, and a surface portion comprising a third amount of Ge which is greater than the second amount.

Abstract: A method of forming a semiconductor circuit having FinFET devices that have fins of different height is provided. There is a shallow trench isolation layer (STI) on top of a semiconductor substrate. A first Fin Field Effect Transistor (FinFET) comprises a first semiconductor fin including a first layer that extends from a common substrate level through the STI layer to a first height above a top surface of the STI layer. There is a second FinFET comprising a second semiconductor fin including the first layer that extends from the common substrate level through the STI layer to the first height above the top surface of the STI layer, plus a second layer having a second height, plus a third layer having a third height. The second semiconductor fin is taller than the first semiconductor fin.

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

Abstract: A semiconductor substrate includes a first-conductivity drift layer, a first-conductivity first impurity layer, a second-conductivity base layer, and a first-conductivity first emitter region. The first impurity layer is provided on the drift layer, and has impurity concentration higher than impurity concentration of the drift layer. The base layer is provided on the first impurity layer. The first emitter region is provided on the base layer. The first impurity layer connects between trenches. The plurality of trenches are formed in the semiconductor substrate covered by a gate insulation film. The gate insulation film has a first thickness between a gate electrode and the drift layer in a side wall surface, and has a second thickness between the gate electrode and the drift layer in a bottom surface. The second thickness is larger than the first thickness.

Abstract: A semiconductor device includes an n-type field effect transistor (nFET) including a first fin and a first metal gate formed on the first fin, and a p-type field effect transistor (pFET) including a second fin and a second metal gate formed on the second fin, a thickness of the second metal gate being substantially the same as a thickness of the first metal gate.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first insulting layer on a substrate, forming a first conductor pattern in the first insulating layer, forming a second insulating layer on the first insulating layer, and forming a second wiring pattern and a contact via in the second insulating layer, wherein a top surface of the first insulating layer is higher than a top surface of the first conductor pattern.

Abstract: Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.

Abstract: Embodiments of a method for forming a staircase structure of 3D memory devices are disclosed. The method comprises (i) forming an alternating layer stack including multiple layers disposed on a substrate in a vertical direction; (ii) removing a portion of the alternating layer stack to form multiple step-platforms in a staircase region of the alternating layer stack; (iii) forming a hard mask layer to cover top surfaces of the step-platforms; (iv) forming multiple openings in the hard mask layer to expose a portion of each of the step-platforms; (v) forming a photoresist layer to cover the top surfaces of the step-platforms and the hard mask layer; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases on each of the step-platforms; (vii) removing the photoresist layer and the hard mask layer; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Abstract: A device emitting mid-infrared light that comprises a semiconductor substrate of GaSb or closely related material. The device can also comprise epitaxial heterostructures of InAs, GaAs, AlSb, and related alloys forming light emitting structures cascaded by tunnel junctions. Further, the device can comprise light emission from the front, epitaxial side of the substrate.

Abstract: A silicon carbide epitaxial film has a plurality of arc-shaped or annular basal plane dislocations and a plurality of threading dislocations. The plurality of threading dislocations have a first threading dislocation which is surrounded by the plurality of basal plane dislocations and a second threading dislocation which is not surrounded by the plurality of basal plane dislocations, when viewed from a direction perpendicular to a main surface. The plurality of basal plane dislocations and the first threading dislocation constitute an annular defect. An area density of the plurality of threading dislocations in the main surface is more than or equal to 50 cm?2. A value obtained by dividing an area density of the annular defect when viewed from the direction perpendicular to the main surface by the area density of the plurality of threading dislocations in the main surface is more than or equal to 0.00002 and less than or equal to 0.004.

Abstract: A semiconductor device includes: a substrate; a drift layer which is disposed on the substrate and has a groove; an underlayer which is disposed above the drift layer; a first opening which penetrates the underlayer to reach the drift layer; an electron transit layer and an electron supply layer which are disposed to cover the first opening; a second opening which penetrates the electron supply layer and the electron transit layer to reach the underlayer; a gate electrode which is disposed above the electron supply layer at a position corresponding to a position of the first opening; a source electrode which is disposed to cover the second opening and in contact with the underlayer; and a drain electrode which is disposed on a backside surface of the substrate. A bottom surface of the groove is closer to the substrate than a bottom surface of the first opening.

Abstract: A module package can include a substrate; at least one device component configured to be positioned on the substrate; a module package lid configured to be positioned over the at least one device component and on the substrate, the module package lid exhibiting a plateau portion; and at least one mounting spring configured to be positioned on the module package lid, wherein the at least one mounting spring is configured to be mechanically coupled with a mounting surface and further positionally secure the module package lid and the at least one device component. Each mounting spring can include a middle portion; an end portion having a mounting hole; and a curved section between the middle portion and the end portion, the middle portion arranged to mate with the plateau portion of the module package lid when the end portion are secured to the substrate, the curved section being configured to prevent contact with a first corner portion of the module package lid.

Abstract: A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed through the group III-V layer, into a semiconductor substrate underlying the group III-V layer, to form a via opening. A doped region is formed in the semiconductor substrate, through the via opening. Further, the doped region is formed with an opposite doping type as a surrounding region of the semiconductor substrate. The through via is formed in the via opening and in electrical communication with the doped region.

Abstract: An array substrate provided comprises a gate insulating layer, touch control element and first conducting wire disposed on a substrate; insulating interlayer covering gate insulating layer, touch control element and first conducting wire; protective wire arranged along the surface periphery of insulating interlayer; planarization layer covering insulating interlayer and protective wire, and second conducting wire disposed on surface of planarization layer; wherein touch control element is insulated from first conducting wire comprising an extension section, and free end of extension section is a first end; protective wire is electrically connected with first end; second conducting wire comprises a second and third end arranged oppositely and a contact position between second and third end; second end is electrically connected with touch control element, and contact position is electrically connected with a portion of first conducting wire inner substrate.