Abstract: A composite bump includes a plurality of first bumps that is metal-bonded to an electrode pad of a semiconductor chip, and a second bump that is metal-bonded to the plurality of first bumps. A method for forming a composite bump, includes forming a plurality of first bumps to be metal-bonded to an electrode pad of a semiconductor chip, and forming a second bump to be metal-bonded to the plurality of first bumps.

Abstract: A high power semiconductor device with a floating field ring termination includes a wafer, wherein a plurality of floating field rings is formed in an edge termination region adjacent to a first main side surface of the wafer. At least in the termination region a drift layer, in which the floating field rings are formed, includes a surface layer and a bulk layer wherein the surface layer is formed adjacent to the first main side surface to separate the bulk layer from the first main side surface and has an average doping concentration which is less than 50% of the minimum doping concentration of the bulk layer. The drift layer includes a plurality of enhanced doping regions, wherein each one of the enhanced doping regions is in direct contact with a corresponding one of the floating field rings at least on a lateral side of this floating field ring, which faces towards the active region.

Abstract: A quantum dot LED includes a first bracket, an LED chip fixed on the first bracket and connected to the first bracket, and a first inorganic barrier layer located on an upper side of the first bracket, wherein the first inorganic barrier layer encapsulates the LED chip on the first bracket. Wherein a groove is formed on the first inorganic barrier layer, a lens disposed above the first inorganic barrier layer and the first inorganic barrier layer enclose the groove into a closed space, and a silica gel body is disposed within the closed space, and multiple quantum dots are dispersed in the silica gel body. The lens and the inorganic barrier layer form a closed space, and the silica gel body is placed therein to perform water-oxygen isolation of the quantum dots. Meanwhile, the lens can scatter the light and ensure the light-emitting effect of the LED.

Abstract: A nitride fluorescent material containing at least one element selected from the group consisting of Ca, Sr, Ba and Mg, at least one element selected from the group consisting of Li, Na and K, at least one element selected from the group consisting of Eu, Ce, Tb and Mn, Al and N is provided, wherein when the maximum value of absorbance in 450 cm?1 or more and less than 900 cm?1 is taken as 1 in an FT-IR spectrum, an integrated value Z1 of a domain surrounded by a base line A connecting absorbance values at 1,200 cm?1 and 1,600 cm?1 and an absorbance spectrum of 1,200 cm?1 or more and less than 1,600 cm?1 is 4.0 or less, and/or an integrated value Z2 of a domain surrounded by a base line B connecting absorbance values at 2,700 cm?1 and 3,680 cm?1 and an absorbance spectrum of 2,700 cm?1 or more and less than 3,680 cm?1 is 5.0 or less.

Abstract: According to one embodiment, a display device includes a first subpixel and a second subpixel. An area, in a plan view, surrounded by a first signal line, a second signal line, a first scanning line, and a second scanning line and including a first pixel electrode is a first area. An area, in a plan view, surrounded by the first signal line, the second signal line, the second scanning line, and a third scanning line and including a second pixel electrode is a second area. The first area has a first distance in the first direction and the second area has a second distance in the first direction. The first distance is greater than the second distance.

Abstract: A chip mounting method includes providing a first substrate including a light transmissive substrate having first and second surfaces, a sacrificial layer provided on the first surface, and a plurality of chips bonded to the sacrificial layer, obtaining first mapping data by testing the chips, the first mapping data defining coordinates of normal chips and defective chips among the chips, disposing a second substrate below the first surface, disposing the normal chips on the second substrate by radiating a first laser beam to positions of the sacrificial layer corresponding to the coordinates of the normal chips, based on the first mapping data, to remove portions of the sacrificial layer thereby separating the normal chips from the light transmissive substrate, and mounting the normal chips on the second substrate by radiating a second laser beam to a solder layer of the second substrate.

Abstract: For the purpose of shortening the MEMS manufacturing TAT, the MEMS manufacturing method according to the present invention includes a step of extracting the first MEMS with first characteristic in a range approximate to the required characteristic from the plurality of MEMS preliminarily prepared on the main surface of the substrate, and a step of forming a second MEMS having the required characteristic by directly processing the first MEMS.

Abstract: The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

Abstract: A method for processing a stack with a carbon based patterned mask is provided. The stack is placed in an etch chamber. A silicon oxide layer is deposited by atomic layer deposition over the carbon based patterned mask by providing a plurality of cycles, wherein each of the cycles of the plurality of cycles, comprises providing a silicon precursor deposition phase, comprising flowing an atomic layer deposition precursor gas into the etch chamber, where the atomic layer deposition precursor gas is deposited while plasmaless and stopping the flow of the atomic layer deposition precursor gas and providing an oxygen deposition phase, comprising flowing ozone gas into the etch chamber, wherein the ozone gas binds with the deposited precursor gas while plasmaless and stopping the flow of ozone gas into the etch chamber. Part of the silicon oxide layer is etched. The stack is removed from the etch chamber.

Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing.

Abstract: A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.

Abstract: Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.

Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

Abstract: A method for producing a semiconductor device includes implanting protons from a rear surface of a semiconductor substrate of a first conductivity type, and after the implanting protons, forming a first semiconductor region of the first conductivity type having a impurity concentration higher than that of the semiconductor substrate by performing an annealing process for the semiconductor substrate in an annealing furnace. The forming a first semiconductor region includes substituting oxygen gas for nitrogen gas in a normal pressure atmosphere, thereby reducing a partial pressure of the oxygen in the annealing furnace, and after the subtracting oxygen gas, performing the annealing process in the annealing furnace with a hydrogen gas atmosphere in a range of 300° C. to 450° C. The hydrogen gas atmosphere includes a volume concentration of hydrogen in a range of 6% to 30%.

Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC also includes a contact layer on the second-side of the bulk semiconductor die. The RFIC further includes a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.

Abstract: Systems, methods, and computer-program products for fluid analysis and monitoring are disclosed. Embodiments include a removable and replaceable sampling system and an analytical system connected to the sampling system. A fluid may be routed through the sampling system and data may be collected from the fluid via the sampling system. The sampling system may process and transmit the data to the analytical system. The analytical system may include a command and control system to receive and store the data in a database and compare the data to existing data for the fluid in the database to identify conditions in the fluid. Fluid conditions may be determined using machine learning models that are generated from well-characterized known training data. Predicted fluid conditions may then be used to automatically implement control processes for an operating machine containing the fluid.

Abstract: Provided is a sheet (2) for forming protective film, including: a protective film-forming film (1) characterized in that the light transmittance thereof at a wavelength of 1600 nm of 72% or more, and the light transmittance thereof at a wavelength of 550 nm of 20% or less; and a release sheet (21) laminated upon one or both faces of the protective film-forming film (1). According to this sheet (2) for forming a protective film, it is possible to form a protective film that allows for the inspection of cracks, etc., on a workpiece or a product obtained by processing the workpiece, while preventing grinding marks on the workpiece or the product from being visible to the naked eye.

Abstract: The present disclosure relates to a technical field of semiconductors and discloses a semiconductor resistor and a manufacturing method therefor.

Abstract: A method includes performing an etching process in a first process module, moving a workpiece formed by the etching process from the first process module to a second process module, and performing a film forming process on the workpiece in the second process module. In the performing the film forming process, an insulating film is formed on a first surface and a second surface of a laminated portion by plasma of a processing gas that contains hydrogen. In the performing the film forming process, an internal pressure of the second process module is 200 mTorr or more, and a hydrogen partial pressure of the second process module is 15 mTorr or less. The performing the etching process, the moving the workpiece, and the performing the film forming process are consistently performed in a state where oxygen is exhausted.