Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.

Abstract: The invention proposes an interposer assembly architecture for noise suppression circuits on the package of a CPU or high power, high frequency VLSI device. In this architecture, charge is stored on dedicated capacitors at a voltage substantially higher than the operating voltage of the VLSI device. These capacitors are mounted upon active circuits that are packaged to match the size and form factor of the capacitors and this assembly is then attached to the package substrate. Charge is conveyed from the capacitor terminals on the backside of the packaged active circuits chip. Depending upon the capacitor construction, these terminals may either be double-sided contact terminals along the edge of the active device's package, or may be feed-through contacts.

Abstract: The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).

Abstract: An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.

Abstract: Semiconductor components having a semiconductor body which includes a semiconductor base surface have to be sealed with a molding compound in order to protect against moisture or heat. Mechanical interlocking of the molding compound to the semiconductor base surface is achieved by means of at least one interlocking structure. This may be either a horizontal interlocking structure for mechanically interlocking the molding compound to the semiconductor base surface in the direction which is horizontal with respect to the semiconductor base surface and/or a vertical interlocking structure for mechanically interlocking the molding compound to the semiconductor base surface in the direction which is vertical with respect to the semiconductor base surface.

Abstract: A light transmissive cover for a device comprising: a cover member of light transmissive material; and a junction member joined to the cover member, the junction member being a member used to be joined to the body of the device and having a light interrupting film on the inner surface thereof. A device provided with a light transmissive cover, the device being provided with a cover member of light transmissive material joined to the body of device via a junction member so as to cover at least a part of the device, and having a light interrupting film on the inner surface of the junction member is also disclosed. In addition, methods for manufacturing them disclosed.

Abstract: An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.

Abstract: The invention relates to a semiconductor component for mounting on a printed circuit board. The semiconductor component includes a housing that at least partially surrounds at least one flat semiconductor chip. Electrical contacts are assigned to the semiconductor chip and serve to establish an electrical connection to electrodes provided on a printed circuit board. The flat semiconductor chip has a mounting lateral surface that includes contact surfaces configured to make contact with the electrical contacts. A buffer layer is located between the housing and the chip, and surrounds the chip up to a supporting surface located on the mounting lateral surface.

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract: The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insulation film, a growth suppression film having an opening whose width is wider than that of the Al wiring is formed on the interlayer insulation film and the Al wiring. In this condition, Al and the like are grown by a selective CVD method and the like. Accordingly, the connection pillar is formed on the Al wiring within the opening, in a self-matching manner with respect to the Al wiring.

Abstract: A holding fixture that holds a component and mounts the component on an electronic circuit board includes a holding member that holds the component at a side of a first surface of the electronic circuit board, a first fixing member that includes a first base that is engageable with the holding member, and an elastic member that is pivotally attached to the base, sandwiches the electronic circuit board at a side of a second surface of the electronic circuit board, and elastically supports the holding member at the side of the first surface, the second surface opposing to the first surface, and a second fixing member that includes a second base that is engageable with the holding member, and a projection member that projects from the second surface of the electronic circuit board and is engageable with the elastic member.

Abstract: A semiconductor package with an encapsulated passive component mainly includes at least a substrate having a surface, a passive component and a molding compound. A plurality of SMD pads (Solder Mask Defined pads) and a solder mask are formed on the surface of the substrate. Each SMD pad has an exposed sidewall portion exposed out of the solder mask. A blocking bar is formed between the exposed sidewall portions of the SMD pads. There is at least a flowing channel formed between the blocking bar and the exposed sidewall portions. The passive component is mounted on the surface of the substrate and connected to the SMD pads, the flowing channel is located under the passive component. It is advantageous to fill the molding compound into the flowing channel.

Abstract: A method of forming an improved seal ring structure is described. A continuous metal seal ring is formed along a perimeter of a die wherein the metal seal ring is parallel to the edges of the die and sloped at the corner of the die so as not to have a sharp corner and wherein the metal seal ring has a first width at the corners and a second width along the edges wherein the first width is wider than the second width.

Abstract: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers (nm). A number of via holes is defined above the seed layer. A layer of copper is deposited over the seed layer using electroless plating to fill the via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times, forming second, third and fourth layers of copper. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided.

Abstract: The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.

Abstract: A chip package including a heat spreader, a circuit substrate, locating structures, a chip, wires, and an encapsulating compound is provided. The heat spreader has a bonding surface, and the circuit substrate is disposed on the bonding surface of the heat spreader. The circuit substrate has an opening, which exposes a portion of the bonding surface. The locating structures are disposed on the heat spreader for fixing the circuit substrate and attaching the circuit substrate to the bonding surface closely. The chip is disposed on the bonding surface exposed by the opening, and the wires are coupled between the chip and the circuit substrate. The encapsulating compound is disposed on the bonding surface exposed by the opening for covering the chip, the wires, and a portion of the circuit substrate. The chip package has high reliability and high yield of processing.

Abstract: A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.

Abstract: A multi-mode integrated circuit structure. In one embodiment, an integrated circuit structure includes a first die having at least one first component disposed on a face, the first die fabricated using a first process that is optimal for operating the component in an first mode and a second die stacked on the first die, the second die having at least one second component disposed on a face and the second die fabricated using a second process separate from the first process that is optimal for operating the second component in a second mode. As such, the integrated circuit structure provides an electronic device with a single integrated circuit structure for performing operations optimally in more than one mode, such as operations in enhancement mode and operations in depletion mode.

Abstract: Disclosed herein are a flip chip type nitride semiconductor light emitting device, which comprises a substrate for growing a nitride semiconductor material, an n-type nitride semiconductor layer formed on the substrate, an active layer formed on at least a part of the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed on the active layer, a bonding force providing layer formed on the p-type nitride semiconductor layer and adapted to provide a bonding force relative to the p-type nitride semiconductor layer, a reflective electrode layer formed on the bonding force providing layer, and adapted to reflect light produced in the active layer toward the substrate and to diffuse electric current, and a cap layer formed on the reflective electrode layer, and adapted to provide a bonding force between the reflective electrode layer and a bonding metal and to reduce contact resistance.

Abstract: A lower electrode of a capacitor element and a wiring are formed in a wiring layer that is one layer below an uppermost wiring layer. Subsequently, after the formation of a capacitance insulating film, a TiN film is formed on the entire surface thereof, and then the TiN film is patterned, thereby forming an upper electrode of a capacitor element and a lead wiring for electrically connecting the upper electrode to a wiring of a third wiring layer. Furthermore, in the uppermost layer, a shield is formed covering the upper portion of the capacitor element.