Abstract: A memory device includes a substrate, an active layer that is spaced apart from the substrate and laterally oriented, a word line that is laterally oriented in parallel to the active layer along one side of the active layer, an active body that is vertically oriented by penetrating through the active layer, a bit line that is vertically oriented by penetrating through the active layer to be spaced apart from one side of the active body, and a capacitor that is vertically oriented by penetrating through the active layer to be spaced apart from another side of the active body.

Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

Abstract: The disclosure provides a thin film transistor, a method of manufacturing the thin film transistor, an array substrate and a display device, belongs to the field of display technology, and can solve the problem that an existing thin film transistor is prone to cracking or breaking due to bending. The thin film transistor of the present disclosure includes a substrate and an active layer arranged on the substrate, and at least one groove is arranged on a surface of the active layer distal to the substrate.

Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

Abstract: Provided is a wafer observation apparatus includes: a scanning electron microscope; a control unit which includes a wafer observation unit that observes a wafer of a semiconductor device, and an image acquisition unit that acquires a wafer image; a storage unit which includes an image storage unit that stores the wafer image and a template image, and a recipe storage unit that stores a wafer alignment recipe including a matching success and failure determination threshold value, an image processing parameter set, and a use priority associated with the template image; and a calculation unit which includes a recipe reading unit that reads the template image and the wafer alignment recipe, a recipe update necessity determination unit that determines update necessity of the wafer alignment recipe, and a recipe updating unit that updates the wafer alignment recipe based on a determination result in the recipe update necessity determination unit.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

Abstract: The present inventive concept relates to a gas distribution apparatus of a substrate processing apparatus including: a first gas distribution module distributing a processing gas to a first gas distribution space; and a second gas distribution module distributing a processing gas to a second gas distribution space which differs from the first gas distribution space, a substrate processing apparatus, and a substrate processing method.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.

Abstract: The present disclosure provides a wiring structure, a preparation method thereof, and a display device. The wiring structure includes a substrate; a pre-arranged layer located on the substrate; and an electrode wiring covering the pre-arranged layer; wherein in the direction perpendicular to an extending direction of the electrode wiring and parallel to a plane on which the substrate is located, an orthographic projection of the pre-arranged layer on the substrate is located within an orthographic projection of the electrode wiring on the substrate, and a side surface of the pre-arranged layer is inclined relative to the plane on which the substrate is located.

Abstract: A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface. A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer.

Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a capacitor including first and second electrodes and a dielectric layer. The dielectric layer may include a zirconium aluminum oxide layer including a first zirconium region adjacent to the first electrode, a first aluminum region, a second aluminum region adjacent to the second electrode, and a second zirconium region between the first and second aluminum regions. The first and second zirconium regions may include zirconium and oxygen and may be devoid of aluminum. The first and second aluminum regions may include aluminum and oxygen and may be devoid of zirconium. The first aluminum region and the first zirconium region may be spaced apart by a first distance, and the first aluminum region and the second zirconium region may be spaced apart by a second distance shorter than the first distance.

Abstract: An LED lamp A includes a plurality of LED modules 2 each including an LED chip 21, and a support member 1 including a support surface 1a on which the LED modules 2 are mounted. The LED modules 2 include a plurality of kinds of LED modules, or a first through a third LED modules 2A, 2B and 2C different from each other in directivity characteristics that represent light intensity distribution with respect to light emission directions. This arrangement ensures that the entire surrounding area can be illuminated with sufficient brightness.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

Abstract: A substrate fixing device includes a baseplate, an insulating layer over the baseplate, and an electrostatic chuck on the insulating layer. The insulating layer includes a heating element and a metal layer. The metal layer has a higher thermal conductivity than the insulating layer and is positioned closer to the electrostatic chuck than the heating element.

Abstract: A system-on-chip (SoC) integrated circuit product includes a machine learning accelerator (MLA). It also includes other processor cores, such as general purpose processors and application-specific processors. It also includes a network-on-chip for communication between the different modules. The SoC implements a heterogeneous compute environment because the processor cores are customized for different purposes and typically will use different instruction sets. Applications may use some or all of the functionalities offered by the processor cores, and the processor cores may be programmed into different pipelines to perform different tasks.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, and relates to the field of display technology. The semiconductor structure includes a substrate. The substrate includes an array region and a peripheral circuit region surrounding the array region. Multiple capacitors are arranged in an array in the array region. Virtual lines connecting centers of any three consecutively adjacent capacitors among the multiple capacitors located at an edge of the array region define a virtual angle greater than 90°.