Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.

Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache using a machine learning module. Performance attributes of system components affected by staging tracks from the storage to the cache are provided to a machine learning module. An output is received, from the machine learning module having processed the provided performance attributes, indicating a staging strategy indicating sectors of a track to stage into the cache comprising one of a plurality of staging strategies. Sectors of an accessed track that is not in the cache are staged into the cache according to the staging strategy indicated in the output.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including: a plurality of memory cells stacked above a substrate, and a plurality of word lines respectively coupled to gates of the plurality of memory cells and extending in a first direction; and a first film including a first area above the memory cell array and a second area different from the first area, and having a compressive stress higher than silicon oxide. In the first area, a plurality of first trenches extending in the first direction are aligned in a second direction that intersects the first direction. In the second area, a second trench in a mesh form is provided.

Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

Abstract: A memory includes a rewritable non-volatile memory cell and input circuitry coupled to the memory cell. The input circuitry, in operation, erases the memory cell in response to reception of a request to read the memory cell. Similarly, a read-once memory includes an addressable, non-volatile memory having a plurality of rewriteable memory cells. Input circuitry coupled to the non-volatile memory responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory.

Abstract: Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

Abstract: Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.

Abstract: A switching resistor comprises a dielectric layer disposed between a first electrode layer and a second electrode layer, the switching resistor having a high resistance state and a low resistance state. The switching resistor is responsive to a voltage bias, applied between the first electrode layer and the second electrode layer, wherein the voltage bias exceeds a threshold to switch from the high resistance state to the low resistance state. The switching resistor is sensitive to photo-illumination to reduce said threshold.

Abstract: Apparatuses and methods for signal line buffer timing control are disclosed. An example apparatus includes a plurality of signal lines including first and second control lines and further including data lines, and further includes first and second signal line buffers. The first signal line buffer includes first driver circuits configured to drive respective data signals on the data lines and to drive first and second control signals on the first and second control lines, respectively. The second signal line buffer includes second driver circuits configured to be activated to receive the data signals. The first and second control signals arrive at the second signal line buffer at different times. The second driver circuits are activated responsive a later one of active first and second control signals and are deactivated responsive to an earlier one of inactive first and second control signals.

Abstract: Apparatuses and techniques are described for reliably storing bad column data in a memory device. Units of bad column data and related units of error detection data are stored in non-adjacent groups of memory cells connected to a word line in a ROM block. A unit of bad column data and a related unit of error detection data can be stored in respective groups of memory cells which are relatively far apart from one another along the word line. This helps ensure that a defect in some NAND strings will not affect both the unit of bad column data and a related unit of error detection data. In another aspect, a unit of bad column data and a related unit of error detection data can be stored using different input/output circuits to further increase robustness.

Abstract: Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.

Abstract: The present disclosure involves a hardware-supported 3D-stacked NVM data compression method and system, involving setting a first identifier to mark a compression state of written-back data, the method at least comprising steps of: dividing the written-back data into a plurality of sub-blocks and acquiring a plurality of first output results through OR operations among the sub-blocks, respectively, or acquiring a plurality of second output results through exclusive OR operations among the sub-blocks, and determining a compression strategy for the written-back data based on the first output results or the second output results; and setting a second identifier to mark a storing means of the written-back data so that the second identifier is in pair with the first identifier, and configuring a storage strategy for the written-back data that includes at least rotating the second identifier.

Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

Abstract: Methods, systems, and devices for low voltage ferroelectric memory cell sensing are described. As part of an access operation for a memory cell, gates of two cascodes may be biased to compensate for associated threshold voltages. An extracted signal corresponding to a charge stored in the memory cell may be transferred through a first cascode to charge a first capacitor. Similarly, a reference signal developed at a dummy digit line may be transferred through a second cascode to charge a second capacitor. By comparing the reference signal developed at the dummy digit line to the extracted signal from the memory cell, the effect of variations in memory cell performance on the sense window may be reduced. Additionally, based on biasing the gates of the cascodes, the difference between the signals compared at the sense component may be low compared to other sensing schemes.

Abstract: Provided is a memory structure including a substrate having a memory region and a peripheral region, a capacitor array, a transistor array, bit lines, and contacts. The capacitor array is on the substrate in the memory region. The transistor array is on and electrically connected to the capacitor array. The bit lines are extended along a row direction in parallel with each other on the transistor array, and are electrically connected to the transistor array. Each of the contacts is connected to one of the bit lines and a conductive device at the substrate in the peripheral region. Each of the contacts includes a first portion, a second portion, and a third portion. The second portion is between the first portion and the third portion. The third portion is electrically connected to the conductive device. Distances between each of the third portions and the memory region are the same.

Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.