Abstract: A processing device of a memory device test resource detects that a memory sub-system has engaged with a first memory sub-system interface port and a second memory sub-system interface port of the memory device test resource. The processing device causes a power supply signal to be transmitted from the memory device test resource to the memory sub-system via the first memory sub-system interface port. The processing device identifies a test to be performed for a memory device of the memory sub-system, where the test includes one or more test instructions to be executed in performance of the test. The processing device causes the one or more test instructions to be transmitted from the memory device test resource to the memory sub-system via the second memory sub-system interface port, where the test is performed by the one or more test instructions executing at the memory sub-system.

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and an interface layer and a damping constant enhancing layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface layer may be structured to reduce metal diffusion and the damping constant enhancing layer includes a material having a relatively high damping constant to suppress switching of the magnetization direction of the pinned layer.

Abstract: A system is provided to receive a first request to write data to a non-volatile storage system, which comprises an MRAM, a NAND, and an HDD. The system allocates a first physical address in the MRAM and writes the data to the MRAM at the MRAM first physical address. In response to determining that the data in the MRAM is not accessed within a first predetermined time period, the system copies the data from the MRAM to the NAND at a NAND physical page address and maps a logical page index associated with the data to the NAND physical page address. In response to determining that the data in the NAND is not accessed within a second predetermined time period, the system copies the data from the NAND to the HDD based on an HDD physical address and maps the NAND physical page address to the HDD physical address.

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

Abstract: A method for dynamic memory scheduling with enhanced bank-group batching is described. The method includes determining a read-bank group-spread of each rank, as a number of bank-groups of each respective rank targeted by at least one read instruction. The method further includes determining a write-bank group-spread of each rank, as a number of bank-groups of each rank targeted by at least one write instruction. The method also includes stalling a current batch of read instructions in a rank when the read-bank group-spread of the rank is less than a predetermined value. The method further includes stalling a current batch of write instructions in a rank when the write-bank group-spread of the rank is less than the predetermined value.

Abstract: A structure of a memory device is described. The structure can include an array of memory cells. A memory cell can include at least one metal-oxide-semiconductor (MOS) element, where a source terminal of the at least one MOS element is connected to a drain terminal of the MOS element. The source terminal being connected to the drain terminal can cause the at least one MOS element to exhibit capacitive behavior for storing electrical energy. A first transistor can be connected to the at least one MOS element, where an activation of the first transistor can facilitate a write operation to the memory cell. A second transistor can be connected to the at least one MOS element, where an activation of the second transistor can facilitate a read operation from the memory cell.

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve data retention. A transition to the odd-even word line erase phase can be triggered when the memory cells pass a first verify test which indicates that the threshold voltages of the memory cells have decreased below a first voltage. Or, the transition can be triggered when a threshold number of erase-verify iterations have been performed. The erase operation may be completed when the memory cells pass a second verify test which indicates that the threshold voltages of the memory cells have decreased below a second voltage which is less than the first voltage.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to word lines, peripheral circuits configured to generate operation voltages to be applied to the word lines, and control logic configured to control the peripheral circuits in response to a program command, a read command, or an erase command. The peripheral circuits include a voltage generator that adjusts a section of threshold voltage distributions of memory cells to be programmed among the memory cells, according to a distance between the word lines.

Abstract: There are provided a memory controller for performing a program operation and a memory system having the memory controller. The memory system includes a memory device including first and second planes each including a plurality of m-bit (m is a natural number of 2 or more) multi-level cell (MLC) blocks; and a memory controller for allocating a first address corresponding to a first MLC block of the m-bit MLC blocks in which first m-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the m-bit MLC blocks in which second m-bit MLC data is to be programmed, and transmitting the allocated addresses and logical page data included in the m-bit MLC data to the memory device. The memory controller differently determines a transmission sequence of the logical page data according to whether the addresses correspond to the same plane among the planes.

Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

Abstract: The present disclosure relates to a method, an apparatus, an electronic device and a computer readable storage medium for accessing static random access memories. The method includes: receiving an access request for data associated with the static random access memories; writing a plurality of sections of the data into a plurality of different static random access memories in an interleaved manner in response to the access request being a write request for the data, each of the plurality of sections having its respective predetermined size; and reading the plurality of sections of the data from the plurality of static random access memories in an interleaved manner in response to the access request being a read request for the data, each of the plurality of sections having its respective predetermined size.

Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache by training a machine learning module. A machine learning module that receives as input performance attributes of system components affected by staging tracks from the storage to the cache and outputs a staging strategy comprising one of a plurality of staging strategy indicating at least one of a plurality of sectors of a track to stage into the cache. A margin of error is determined based on a current value of a performance attribute and a threshold of the performance attribute. An adjusted staging strategy is determined based on the margin of error. The machine learning module is retrained with current performance attributes to output the adjusted staging strategy.

Abstract: A method is disclosed for optimizing the power flow in an electric power network including a plurality of buses interconnected by transmission lines, and locally connected to loads, generators, and storage devices, the method executing an interior point optimisation algorithm in a computer system to solve an optimal control problem, which is defined over a time period of interest T, and is associated with an objective function representing the total fuel consumption of the generators for the time period of interest T, wherein the objective function depends on a plurality of parameters of the network, such as bus voltages, generator, and storage device powers. the parameters of the network allowed to vary over a large number N of predefined time intervals, each of duration ?t, obtained by subdivisions of the time period of interest T and is subject to network constraints.

Abstract: Various implementations described herein are directed to device having a clock generator that provides write reference signals. The device may include a voltage divider that receives the write reference signals and provides an output reference signal based on write polarity of the write reference signals. The device may include a voltage regulator that receives the output reference signal and provides a regulated voltage to a load based on the output reference signal.

Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.