Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

Abstract: A memory controller may be configured with command logic that is capable of sending a memory access command having incomplete address information via a command/address bus that connects the memory controller to memory modules. The memory controller may send the memory access command via the bus for accessing data stored at memory locations of the memory modules. The memory locations may correspond to different near-memory generated reflecting that the data is not address aligned across the memory modules. Nonetheless, because of the near-memory address generation, the memory controller can send the memory access command having incomplete address information for accessing the data stored at the different addresses, as opposed to having to send multiple memory access commands specifying complete address information on the bus for accessing the data at the different addresses, thereby conserving usage of the available bus bandwidth, reducing power consumption, and increasing compute throughput.

Abstract: A memory system may include: one or more normal memory regions; one or more spare memory regions; and a controller suitable for controlling the normal memory regions and the spare memory regions. The controller may determine, among the normal memory regions, a first normal cell region that includes a concentrated cell region whose access count exceeds a first threshold and neighboring cell regions in a set range from the concentrated cell region perform first address mapping to map an address of the first normal cell region to an address of a first spare cell region in the spare memory regions, and perform second address mapping to map the address of the first spare cell region to an address of a second normal cell region in the normal memory regions, when an access count of the first spare cell region exceeds a second threshold.

Abstract: A read latency reduction method includes receiving a read request sent by a host, where the read request includes location indication information of requested data, obtaining, from read voltage management information based on a first physical location indicated by the location indication information, a read voltage corresponding to a first storage area in which the first physical location is located, the flash array includes a plurality of storage areas, the read voltage management information includes a correspondence between a storage area and a read voltage, and the read voltage in the read voltage management information is dynamically updated, and obtaining the requested data based on the read voltage corresponding to the first storage area, and sending the requested data to the host.

Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.

Abstract: One aspect of this description relates to a memory cell including a first layer including a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure. The memory cell includes a second layer including a first active structure and a second active structure. The first gate structure overlaps the first active structure to form a first access transistor, the second gate structure overlaps the first active structure to form a first pull-down transistor, the third gate structure overlaps the first active structure to form a second pull-down transistor, and the fourth gate structure overlaps the first active structure to form a second access transistor. The second gate structure overlapping the second active structure to form a first pull-up transistor, the third gate structure overlapping the second active structure to form a second pull-up transistor.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a first direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).

Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.

Abstract: A memory cell arrangement is provided that may include: at least one memory cell and a read-out circuit. The memory cell includes a first terminal, a second terminal, a third terminal, and a field-effect transistor structure being connected to the first terminal, the second terminal, and the third terminal. The read-out circuit is configured to carry out a read-out operation to read out a memory state of the memory cell, the read-out operation including: providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated, and sensing the leakage current to determine the memory state of the memory element.

Abstract: Techniques described herein are related to spread amplifier having a differential amplifier spread (DAS) configured to receive a pair of input signals and to provide a plurality of graded outputs each having different output levels. The spread amplifier further includes a final driver stage having a plurality of final drivers, wherein each of the final drivers is configured to receive a respective one of the plurality of graded outputs. The spread amplifier may be used for the regulation of various voltages such as VDQS and VARY.

Abstract: A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.

Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.

Abstract: A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

Abstract: A method and apparatus for performing automatic power control in a memory device are provided. The method includes: during an initialization phase of the memory device, performing signal level detection on a reference clock request signal to determine whether the reference clock request signal is at a first predetermined voltage level or a second predetermined voltage level, for performing the automatic power control for the memory device, wherein the reference clock request signal is received through an IO pad; and according to a logic value carried by an input signal of a selective regulation circuit (SRC), performing selective power control to generate a secondary power voltage according to a main power voltage, wherein the selective power control makes the secondary power voltage be either equal to the main power voltage or a regulated voltage of the main power voltage in response to the logic value carried by the input signal.

Abstract: An inversion signal generation circuit may include a transition detection signal generation circuit suitable for generating first to fourth transition detection signals, a first XOR gate suitable for receiving a fourth inversion signal and the first transition detection signal, and generating a first pre-inversion signal, a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal, a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal, a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal, a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal, and a first alignment circuit suitable for generating first to fourth inversion signals.

Abstract: A processing device of a memory device test resource detects that a memory sub-system has engaged with a first memory sub-system interface port and a second memory sub-system interface port of the memory device test resource. The processing device causes a power supply signal to be transmitted from the memory device test resource to the memory sub-system via the first memory sub-system interface port. The processing device identifies a test to be performed for a memory device of the memory sub-system, where the test includes one or more test instructions to be executed in performance of the test. The processing device causes the one or more test instructions to be transmitted from the memory device test resource to the memory sub-system via the second memory sub-system interface port, where the test is performed by the one or more test instructions executing at the memory sub-system.

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.