Abstract: A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for detecting a number of error bits from data stored in the plurality of pages; summing the number of error bits; generating a bad word line list based on the sum of the error bits; and performing a test read operation on the plurality of pages based on the bad word line list.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

Abstract: Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.

Abstract: An environment control apparatus includes an apparatus body, a processing device, a plurality of heating devices, and a plurality of cooling devices. The apparatus body includes a plurality of accommodating chambers each having one of the heating devices or one of the cooling devices. Each of the heating devices has a high temperature contacting structure, and each of the cooling devices has a low temperature contacting structure. When a chip testing device carrying chips is arranged in one of the accommodating chambers, the chip testing device is supplied with electricity, and the heating device or the cooling device of the one of the accommodating chambers is in operation, the chip testing device is configured to test the chips disposed thereon.

Abstract: A method and apparatus for a CTC data copy operation, in that modification, and subsequent encoding only affects a small portion of metadata associated with copied data. By modifying and re-encoding only this small portion of metadata, a small portion of the parity data for the copied data requires updating. In embodiments where there are no errors in the read data to be copied (e.g., from an SLC portion of a NAND), decoding, modification, and encoding, may be done in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits may be predetermined and combined (e.g., by XOR) to update the metadata parity bits.

Abstract: A control method for a memory device uses an inverting data to label that a data stored in a memory block is in an inverting state or a non-inverting state. According to the inverting data, the number of bits whose data states is changed is lower than a half of total bits in the memory block in writing operation. Therefore, an energy consumption of the memory device can reduce. The control method of the present invention also can utilize the inverting data to label a memory block with a defective bit and to select a spare block to repair the memory block with a defective bit.

Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

Abstract: A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.

Abstract: A software-defined linear feedback shift register (SLFSR) implements a low-power test compression for launch-on-capture (LOC). Each bit of an extra register controls a stage of the SLFSR. A control vector is shifted into the extra register to indicate whether a primitive polynomial contains the stage of the non-zero bit. Therefore, SLFSR can configure any primitive polynomials with different degrees by loading different control vectors without any hardware overhead. A low-power test compression method and design for testability (DFT) architecture provide LOC transition fault testing by using seed encoding scheme, low-power test application procedure and a software-defined linear-feedback shift-register (SLFSR) architecture. The seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set.

Abstract: An apparatus and method are provided for executing debug instructions. The apparatus has processing circuitry for executing instructions fetched from memory, and a debug interface. The processing circuitry is responsive to a halt event to enter a halted mode where the processing circuitry stops executing the instructions fetched from memory, and instead is arranged to execute debug instructions received from a debugger via the debug interface. The processing circuitry is responsive to detection of a trigger condition when executing a given debug instruction to exit the halted mode transparently to the debugger, and to take an exception in order to execute exception handler code comprising a sequence of instructions fetched from memory. On return from the exception, the processing circuitry then re-enters the halted mode and performs any additional processing required to complete execution of the given debug instruction.

Abstract: The present invention relates to the technical field of integrated chips, and more particularly, to a system-level test method for a flash memory. The method comprises: step S1, providing a test flag file, and storing a test number parameter in the test flag file; step S2, determining whether a value of the test number parameter reaches a pre-set value; if not, turning to step S3; if yes, ending and counting a verification result; step S3, performing one partition mirror data check on all partitions of the flash memory, and performing one file data check on a current system file of the flash memory; and step S4, restarting a test device, subtracting one from the value of the test number parameter, and returning to step S2.

Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative LDPC correction process, wherein at least one iteration after a first iteration in the LDPC correction process uses a criterion based at least partially on a previous iteration or partial iteration.

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.

Abstract: A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).

Abstract: A semiconductor integrated circuit reads data from a memory, which stores the data including a data portion and a parity bit, and makes an error correction to the data. The semiconductor integrated circuit includes a memory controller for reading the data from the memory; and an error correction controller having an error correction circuit having the ability to correct a predetermined number of bits of errors. The error correction controller applies an error correction to the read data by the error correction circuit, and determines whether all errors contained in the data are corrected, based on the data portion and the parity bit of the data after the error correction. When not all the errors contained in the data are determined to be corrected, the error correction controller applies an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

Abstract: A method includes programming data in a block of a storage device, and reading back the programmed data and determining a maximum error count for the block. A code rate index that satisfies correction of the maximum error count for the block is determined. A current code rate index is adjusted to the code rate index that satisfies correction of the maximum error count for the block.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.

Abstract: A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies the threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executes the operation at the increased drive strength value of the storage device.

Abstract: A determination is made that bit errors of a selected data chunk stored in a computer memory are unable to be completely corrected using an initial error correction scheme. A plurality of other data chunks sharing a physical layout structure element of the computer memory with the selected data chunk is analyzed to identify one or more likely bit error locations of the selected data chunk aligned with one or more corresponding bit error locations of a threshold number of the analyzed other data chunks. An attempt is made to correct the bit errors of the selected data chunk based on the identified one or more likely bit error locations of the selected data chunk.