Abstract: A Burn-In Board (BIB) transfer module links a Burn-In Board (BIB) Loader/Unloader (BLU) to a burn-in chamber rack. The BIB transfer module is capable of transferring a BIB between the BLU and the burn-in chamber rack by moving the BIB in at least two perpendicular directions while minimizing the physical footprint required by the BIB transfer module. The BIB transfer module supports slot level burn-in of components as opposed to batch level burn-in because the burn-in chamber rack may begin the burn-in process as soon as a BIB is delivered to an individual chamber slot in the burn-in chamber rack. The BIB transfer module may easily be detached and separated from the BLU and the burn-in chamber rack without affecting the continuing operation of the BLU and the burn-in chamber rack.

Abstract: A defect inspection apparatus is provided which allows a technology for inspecting a pattern on a wafer by using an electron beam to implement a high-resolution and higher-speed inspection. A semiconductor wafer is irradiated with an electron beam and electrons reflected in the vicinity of the wafer are detected. The presence or absence of a defect and the location thereof are measured by forming an image from only a component which changes with a periodicity larger than a size of a circuit pattern or the repetition periodicity thereof by using lenses and comparing an image signal with a preset value.

Abstract: The present invention relates to a semiconductor test interface for interfacing a DUT (Device Under Test) to a pin card using a cable comprising a DUT board including one or more first connectors for electrically connecting one or more test sockets for mounting the DUT to the one or more cables, and a circuit wiring for electrically connecting the one or more test sockets to the one or more first connectors; and the one more cable including a second connector for an electrical connection to the one or more first connectors, and a third connector for an electrical connection to the pin card, wherein the one or more first connectors correspond to the one or more cables by 1:1. In accordance with the present invention, the manufacturing cost is reduced by simplifying the manufacturing process and the semiconductor test interface may easily correspond to the test of the different DUTs.

Abstract: A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.

Abstract: A testing apparatus and method for testing integrated circuits is disclosed wherein a device under test is continuously maintained at a desired set point temperature by an included thermal body. The thermal body has an enclosed phase change material which provides latent heat to the device under test such that there is negligible temperature variation realized by integrated circuits being tested.

Abstract: A direct current and a modulation signal are simultaneously applied to contact pads on a device under test, such as a laser diode, with a probe that reduces signal distortion and power dissipation by transmitting a modulated signal through an impedance matching resistor and transmitting of a direct current over a second signal path that avoids the impedance matching resistor.

Abstract: A fixed filter assembly kit includes a plurality of filters with associated terminals inside a case. A booklet disclosing which filters are associated with which terminals as well as technical information about each filter is includes inside the lid. When the case lid is opened, the terminals are available to a user to perform proof of performance testing on a CATV system.

Abstract: The present invention relates to a probe card that a probe of the probe card is movable only in a vertical direction using a trench to improve a electrical or a mechanical characteristic and to automatically limit the vertical movement thereof within a predetermined range. A pitch may be reduced so as to correspond to a decreasing distance between pads. A flatness of a probe tip may be maintained within a few micrometers using a semiconductor manufacturing process. 32 simultaneous parallel testing is possible contrary to a convention probe card. A wafer level testing is possible, and time and cost for a wafer testing are reduced.

Abstract: A method of measuring at least one electrical property of a semiconductor wafer includes providing an elastically deformable and electrically conductive contact having an insulative oxide layer formed on an exterior surface thereof by a controlled oxidation process, such as, without limitation, thermal oxidation, anodic oxidation or deposition oxidation. A first electrical contact is formed between the oxide layer on the surface of the contact and a dielectric layer overlaying a top surface of the semiconductor wafer and a second electrical contact is formed with the semiconductor wafer. A CV type stimulus is applied between the first electrical contact and the second electrical contact. A response of the semiconductor wafer to the CV type stimulus is measured and at least one electrical property of the dielectric layer, the semiconductor wafer or both is determined from the response.

Abstract: Provided is an inspection device which inspects a thin film transistor (TFT) for supplying a current to a light emitting element. The inspection device includes: a first current supply circuit which supplies a drain current between a drain and a source of the TFT; a gate voltage adjustment circuit which adjust a gate voltage to be applied to a gate of the TFT so as to allow a predetermined specified current to flow between the drain and source of the TFT; and a measurement unit which measures the gate voltage adjusted by the gate voltage adjustment circuit.

Abstract: A device for testing thin elements, such as wafers or individual substrates, while at the same time offering a facility for inspecting the reverse side of the thin elements is provided in which any deflection of the substrate as a consequence of high contact power of the probe card is avoided and which is also suitable for substrate diameters of 200 mm and above. The device includes a stable plate with a central opening positioned on the basic construction, a frame which can be moved and/or turned on the plate in an x/y direction and, if required, in a theta direction, a highly-rigid substrate support which can be mounted in the frame, and substrates which can be mounted on the substrate support, wherein the mounting is effected through a vacuum, using mechanical elements (clamping ring, clamping foil or other suitable clamping elements), gel pack pads, or adhesive etc.

Abstract: The device for measuring the intensity (1) of a strong current passing through a wire (1) comprises a magnetic sensor (2) in the form of a loop surrounding the wire (1), and a turn (3) of conductive material surrounding the wire (1) conducting a high-frequency counter-current, the intensity of which is adjusted to cancel the magnetic field (H) is characterized in that the turn (3) of conductive material is in short circuit and surrounds the magnetic sensor (2).

Abstract: A probe apparatus has first and second access ports and a measurement port. The first and second access ports are adapted to be interposed in a test circuit. A voltage amplifier and a voltage splitter are adapted to present the second access port and the measurement port each with a voltage representative of a voltage received by the first access port.

Abstract: Devices that couple to high voltage transmission lines obtain power themselves using the body capacitance of an element of the devices. The devices generate a comparatively lower voltage from the current flowing between the high voltage line and the element of the device that generates the body capacitance. The devices can be used to operate sensors that monitor the transmission lines or parameters of the power distribution system, such as current, line temperature, vibration, and the like. The devices can also be used as indicators, such as aircraft warning lights, information signs, etc. In addition, the devices can operate as RF transmission/reception or repeater devices, radar devices, mesh networking nodes, video/audio surveillance, sound emitting devices for scaring animals, drones that traverse the power line, etc. Because the devices operate in response to line voltage rather than current, the devices are reliable even in low current conditions.

Abstract: The present invention is an elastic seal for use with a sanitary probe. The elastic seal forms a layer between the probing member and the coating member to eliminate the formation of voids between the two. The elastic seal may include an elastic substance, such as silicon or rubber, to enable it to remain in contact with both the probing member and the coating member in the case that a change in temperature causes either or both to expand or contract. The elastic seal may have a coefficient of thermal expansion that is intermediate to a coefficient of thermal expansion of the probing member and a coefficient of thermal expansion of the coating member. The elastic seal prevents voids from forming in the probe assembly into which outside materials may enter.

Abstract: A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.

Abstract: A method of testing for power and ground continuity of a semiconductor device having Input and Output (IO) pins and at least a pair of power and ground pins includes identifying the power and ground pins of the device. A victim pin is selected from the IO pins of the device for each pair of the power and ground pins, and an aggressor pin for each victim pin is selected from the remaining IO pins. The aggressor pins are toggled between a high state and a low state. A level of switching noise on each victim pin is measured, and the measured levels of switching noise are compared with predetermined data to determine power and ground continuity of the device.

Abstract: The present invention provides an inspection apparatus for circuit board for conducting electrical inspection by electrically connecting inspection object electrodes of the circuit board to a plurality of inspection electrodes formed in accordance with a pattern corresponding to the inspection object electrodes through an anisotropically conductive sheet, wherein each of an upper-side board-compressing member and a lower-side board-compressing member respectively arranged on an upper side and lower side of the inspection object circuit board is provided on upper-side base plate and lower-side base plate supported by a plurality of supports of support-infixing plates, and an upper-side supporting point and a lower-side supporting point corresponds to the respective supports on the respective base plates are arranged at positions different from each other on a plane of projection in a thickness-wise direction of the upper-side board-compressing member and lower-side board-compressing member when the inspection

Abstract: To achieve the foregoing, and in accordance with the purpose of the present invention, a method and apparatus for testing individual power and ground pins on a semiconductor integrated circuit are disclosed. The method and apparatus includes organizing the power pins of the die into a first group of power pins and a second group of power pins. Each of the first group of power pins are then connected through a first set of resistors to a first common node, and each of the second group of power pins through a second set of resistors to a second common node respectively. A voltage is next applied between the first and second nodes. The voltage at each of the first group of pins is compared with a first threshold voltage and the voltage at each of the second group of pins is compared with a second threshold voltage. Individual bad pins in the first and second groups are identified based on the comparison.

Abstract: The present invention provides an LSI inspection method and a defect inspection data analysis apparatus capable of shortening a time needed for a wafer test. In a first database 11 is stored inspection data obtained when each defect inspection apparatus 20 inspects a wafer for defects in the front-end process. In a second database 12 are stored non-conforming article judgment criteria for each predetermined type of defect, according to which a non-conforming chip is judged. A defective chip identifying portion 16 identifies a chip having a defect and identifies the type of defect for each defect that the identified chip has, on the basis of the inspection data. For each identified chip, a non-conforming chip judging portion 17 judges whether the chip is a non-conforming article or not according to the non-conforming article judgment criteria corresponding to the type of defect for each defect, and obtains position information within the wafer surface of a chip judged as being a non-conforming article.