Patents Examined by Ha Tran Nguyen
  • Patent number: 7321234
    Abstract: A test probe tip constructed substantially from resistive material. The resistive material is made of resistive conducting material substantially enclosed in and dispersed throughout encapsulating material. The test probe tip has a probing end for probing electronic circuitry and a connection end for interfacing with a probing head. The resistive conducting material forms at least one path through the encapsulating material from the probing end to the connection end. The resistive conducting material may be a plurality of longitudinally-extending resistive/conductive members or a plurality of particulate resistive/conductive members.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: January 22, 2008
    Assignee: LeCroy Corporation
    Inventors: Julie A. Campbell, Lawrence W. Jacobs
  • Patent number: 7319335
    Abstract: An improved prober for an electronic devices test system is provided. The prober is “configurable,” meaning that it can be adapted for different device layouts and substrate sizes. The prober generally includes a frame, at least one prober bar having a first end and a second end, a frame connection mechanism that allows for ready relocation of the prober bar to the frame at selected points along the frame, and a plurality of electrical contact pins along the prober bar for placing selected electronic devices in electrical communication with a system controller during testing. In one embodiment, the prober is be used to test devices such as thin film transistors on a glass substrate. Typically, the glass substrate is square, and the frame is also square. In this way, “x” and “y” axes are defined by the frame.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: January 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Matthias Brunner, Shinichi Kurita, Ralf Schmid, Fayez (Frank) E. Abboud, Benjamin Johnston, Paul Bocian, Emanuel Beer
  • Patent number: 7319337
    Abstract: A control unit of a wafer prober for implementing wafer examination, using a probe card including a multiple number of probes, executes a multiple number of measuring operations by bringing the probes of the probe card into contact with bonding pads formed on a wafer and by measuring the electric characteristics between predetermined pads of the bonding pads, each of the measuring operations being implemented after varying the relative position between the probe card and the wafer, in directions parallel to the face of the wafer. The control unit, upon execution of each of the measuring operations, implements the measuring operation after adjusting the relative position between the probe card and the wafer so that the contact position of each probe of the probes against each pad of the bonding pads is separated from all the positions at which the probes have already touched that pad of the bonding pads for a predetermined number of different times.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: January 15, 2008
    Assignee: Elpida Memory, Inc.
    Inventor: Toru Sakata
  • Patent number: 7319336
    Abstract: An apparatus including a positioner control device, a measuring device and a control routine. The positioner control device is communicatively coupled to a chamber of a charged particle beam device (CPBD) and is configured to individually manipulate each of a plurality of probes within the CPBD chamber to establish contact between ones of the plurality of probes and corresponding ones of a plurality of contact points of a sample positioned in the CPBD chamber. The measuring device is communicatively coupled to the CPBD and the positioner control device and is configured to perform one of a measurement and a detection of a characteristic associated with one of the plurality of contact points. The control routine is configured to at least partially automate control of at least one of the CPBD, the positioner control device and the measuring device.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: January 15, 2008
    Assignee: Zyvex Instruments, LLC
    Inventors: Christof Baur, Robert J. Folaron, Adam Hartman, Philip C. Foster, Jay C. Nelson, Richard E. Stallcup, II
  • Patent number: 7317311
    Abstract: A plurality of wafers each having a conductive film on each face thereof are housed in slots of a cassette, and a potential of “H” level is applied from a control box to each wafer via an electrode. A conductive suction part of a vacuum pincette is connected to a grounding potential. A LED corresponding to the wafer to be operated on is lit up by a specification from a computer so that an operator operates on the wafer specified by the computer using the vacuum pincette. The control box detects the potential of each electrode and decides as to whether a given wafer is correctly operated on or not. In the case of erroneous operation, such an erroneous operation is displayed by means of a buzzer, and an overall result of operation is stored in the computer.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: January 8, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirohito Inoue
  • Patent number: 7315361
    Abstract: An illumination system is disclosed for use in a semiconductor wafer back side inspection assembly. The illumination system includes an illumination source that is configured to direct illumination toward a highly reflective and directionally reflective surface at an angle ? of about 45 degrees to about 75 degrees with respect to the surface.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: January 1, 2008
    Assignee: GSI Group Corporation
    Inventors: Rainer Schramm, Jonathan Ehrmann
  • Patent number: 7315163
    Abstract: In order to correct an overflow of a multiplication result while improving the operation speed, an overflow detection unit detects an overflow based on whether a multiplicand A and a multiplier B are both a negative value with the largest absolute value. A carry-save adder adds together in carry-save addition partial products and ?1 (where all bits are 1) as a first correction value to output an intermediate sum and an intermediate carry corresponding to A×B?1. A carry-propagate adder adds together in carry-propagate addition the intermediate sum, the intermediate carry and a second correction value to output the multiplication result. Where there is no overflow, the second correction value becomes 1 to cancel out the first correction value, whereby the operation result is A×B. Where there is an overflow, the second correction value becomes 0, whereby the operation result is A×B?1 in which the overflow is corrected by the first correction value.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: January 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Daisuke Takeuchi
  • Patent number: 7315177
    Abstract: A mixed signal integrated circuit with self test capability in which a portion of the digital circuitry, during substantially mutually exclusive time intervals, controls self test functions within the analog circuitry and performs digital signal processing functions in conjunction with the remaining portion of the digital circuitry.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: January 1, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Ulrich Seif
  • Patent number: 7312623
    Abstract: A method, system, and apparatus for testing one or more micro-magnetic switches on a wafer is described. A magnet is positioned adjacent to a first switch on the wafer. A probe card is positioned adjacent to the first switch. The probe card mounts a first set of probes and a second set of probes. The first set of probes interface with contact areas of a coil associated with the first switch. The second set of probes interface with conductors on the wafer associated with the cantilever of the first switch. A current source is electrically coupled to the first set of probes. The current source activates the coil of the first switch using the first set of probes to switch the cantilever from a first state to a second state. A switch state monitor is electrically coupled to the second set of probes. The switch state monitor determines whether the cantilever of the first switch is in the first state prior to the current source activating the coil of the first switch.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: December 25, 2007
    Assignee: Schneider Electric Industries SAS
    Inventors: Cheng Ping Wei, Jun Shen
  • Patent number: 7312622
    Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: December 25, 2007
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Robert M. Glidden, Andrew Edward Horch, Jay A. Kuhn, Ronald A. Oliver
  • Patent number: 7312617
    Abstract: Method and apparatus for electrical testing of a device under test (DUT) that employs a connection board with signal contacts for applying test signals and a space transformer that has low pitch contacts arranged on one or more circumferential shelves that define an enclosure in the space transformer. The apparatus has a substrate with fine pitch contacts positioned such that these are within the enclosure. A set of wire bonds is used for pitch reduction by interconnecting the fine pitch contacts with the low pitch contacts arranged on the shelves. The probes are connected to the fine pitch contacts and are used to apply the test signals to a DUT by contacting its pads. In some embodiments, the fine pitch contacts may be embodied by plugs or by blind metal vias.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: December 25, 2007
    Assignee: MicroProbe, Inc.
    Inventor: January Kister
  • Patent number: 7312606
    Abstract: A method for detecting an abnormal condition of a MOS transistor in a subthreshold region. The method includes measuring a variation in a drain current with respect to a variation of a gate voltage of the MOS transistor to obtain a characteristics curve, and calculating, with reference to the obtained characteristics curve, a variation of transconductance with respect to each of the gate voltages to obtain a transconductance variable curve. The transconductance variable curve is differentiated. A number of inflection points in a curve obtained by the differentiation is determined to indicate the abnormal condition of the MOS transistor.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 25, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Soo Jang
  • Patent number: 7312605
    Abstract: An AC power supply testing method upon booting a main board is provided. The testing method is applied to a main board, a microprocessor is in connection with the main board, and a relay is connected with the microprocessor, an AC power supply and a system power supply of the main board. The testing method includes steps of (1) configuring a system power on/off time of the microprocessor; (2) counting down the system power on/off time; (3) determining the current state of the relay; (4) shutting off the relay and resuming executing step (1) if the current state is ON; and (5) executing a power supply testing upon booting if the current state is OFF.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: December 25, 2007
    Assignee: Lite-On Technology Corp.
    Inventors: Kun Sheng Chang, Pao Jen Chen, Anpang Hsieh, Li An Huang
  • Patent number: 7312625
    Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: December 25, 2007
    Assignee: Xilinx, Inc.
    Inventors: Sunhom Paak, Hsung Jai Im, Boon Yong Ang, Jan L. de Jong
  • Patent number: 7309981
    Abstract: A first spring 54 is provided between a support member 51 driven in the Z-axis direction and a heat block 53, and biases the support member 51 and the heat block 53 in the direction of separating them from each other. A second spring 57 is provided between a first pusher 55 for pressing a die 81 of an IC device 8 and a second pusher 56 for pressing a substrate 82 of the IC device 8, and biases the first pusher 55 and the second pusher 56 in the direction of separating them from each other.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: December 18, 2007
    Assignee: Advantest Corporation
    Inventor: Tsuyoshi Yamashita
  • Patent number: 7309991
    Abstract: A pair of pads is formed on an insulating layer formed on a top surface of a substrate, and a plurality of through-holes is laid out at equal intervals between the pads. Adjoining through holes are connected alternately by upper-layer wire interconnect lines exposed on the insulating layer or lower-layer wire interconnect lines buried in the insulating layer, thus constituting a check pattern. A DC power supply is connected between the pair of pads, and a constant current is supplied to a chain pattern of the through holes. Two probes move on a chip surface along the chain pattern of the through holes while keeping a given interval spacing. The probes sequentially scan the upper-layer wire interconnect lines exposed through the chip surface of the chain pattern of the through-holes.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: December 18, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Yorinobu Kunimune
  • Patent number: 7309996
    Abstract: A contactor configured to be electrically connected to the terminals of an electronic component is disclosed. The connector includes multiple contact electrodes contacting the terminals of the electronic component and multiple elastic electrodes each composed of an electrically conductive elastic body. The elastic electrodes generate a pressing force for pressing the contact electrodes against the terminals of the electronic component. The contact electrodes are separable from the elastic electrodes.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: December 18, 2007
    Assignee: Fujitsu Limited
    Inventors: Kazuhiro Tashiro, Shigeyuki Maruyama, Daisuke Koizumi, Takumi Kumatabara, Keisuke Fukuda
  • Patent number: 7310001
    Abstract: A current sensing device for sensing current flowing through a MOSFET has a voltage divider circuit composed of a series circuit of a first resistor and a second resistor having different resistance temperature coefficients, with a voltage division ratio designed to change depending on temperature. The sensing device is connected between a source and a drain of said MOSFET. A sensing circuit takes out the source-to-drain voltage divided with the voltage divider to sense the current flowing through the MOSFET.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: December 18, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Shigeta, Shinichi Fujino, Keita Hashimoto, Sadashi Seto
  • Patent number: 7310002
    Abstract: A method of measuring the counter-electromotive force of the motor accurately is disclosed. The counter-electromotive force of the motor changes with the rotational position and the rotational speed. The value of the counter-electromotive force measured during the inertial rotation is a value associated the simultaneous change of the rotational position and the rotational speed and required to be corrected. The change rate of the rotational speed is set as a deceleration function, and the data are statistically processed using the measurement value of the counter-electromotive force at minuscule time intervals. In this way, the error elements are eliminated for each motor measured thereby to determine the corrected counter-electromotive force at a predetermined rotational speed. Even a miniature motor rapidly decreased in speed can be accurately measured within a short time.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: December 18, 2007
    Assignee: Nidec Corporation
    Inventor: Takuro Iguchi
  • Patent number: 7307437
    Abstract: A plurality of conductive pads of an apparatus in one example are disposed on a circuit board in a predetermined arrangement compatible with an arrangement of probes on an external test connector. One or more of the plurality of conductive pads is disposed on an embedded layer of the circuit board.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: December 11, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert Dobbs, Sachin Navin Chheda, Nitin Bhagwath