Patents Examined by Ha Tran Nguyen
-
Patent number: 7332926Abstract: Good device PASS/FAIL determination is realized by measuring timings of a cross point of differential clock signals CLK and a data signal DATA output from a DUT, and obtaining a relative phase difference between both signals. A semiconductor test apparatus comprises differential signal timing measurement means for outputting cross point information Tcross obtained by a timing of a cross point of one of differential signals, non-differential signal timing measurement means for outputting data change point information Tdata obtained by a timing of transition of a logic of the other non-differential signal output, phase difference calculation means for outputting a phase difference ?T between the cross point information Tcross and the data change point information Tdata, and PASS/FAIL determination means for determining PASS/FAIL of a relative positional relationship of the DUT based on a predetermined threshold value.Type: GrantFiled: July 14, 2006Date of Patent: February 19, 2008Assignee: Advantest Corp.Inventors: Masatoshi Ohashi, Toshiyuki Okayasu
-
Patent number: 7330040Abstract: Method and apparatus for testing a plurality of devices on a device wafer. One embodiment provides a test circuitry wafer having a first surface and a second surface, the test circuitry wafer comprising a plurality of contact pads disposed on the first surface for contacting a plurality of device pads on the device wafer, a plurality of interface pads disposed on the second surface for contacting probe needles on a probe card and one or more test features disposed in the test circuitry wafer, wherein the one or more test features are electrically connected to at least one of the contact pads and the interface pads.Type: GrantFiled: June 25, 2004Date of Patent: February 12, 2008Assignee: Infineon Technologies AGInventor: David Suitwai Ma
-
Patent number: 7330037Abstract: In an electrical characteristic measuring probe of the present invention constructed by assembling a plurality of probe parts, each comprising a base portion, a plurality of terminal portions extended outward from one end of the base portion, wiring patterns extended from a plurality of terminal portions onto the base portion respectively, and contact portions connected to the wiring patterns respectively, a plurality of thin plate-like probe parts are aligned such that respective thin-plate surfaces are placed in parallel with each other and the contact portions are directed in the same direction, and a plurality of probe parts and spacers are fixed by fixing means in a state that the spacer is arranged between a plurality of probe parts respectively.Type: GrantFiled: November 4, 2004Date of Patent: February 12, 2008Assignee: Shinko Electric Industries Co., LtdInventors: Naoyuki Koizumi, Akinori Shiraishi, Kei Murayama
-
Patent number: 7330038Abstract: In one embodiment, a probe card includes a substrate and a plurality of probes. Each of the probes may have a supported portion and an unsupported portion that meet at a base. The unsupported portion may have a non-uniform (e.g. triangular) cross-section along a length that begins at the base. The probes may be interleaved and fabricated using MEMS fabrication techniques.Type: GrantFiled: December 7, 2005Date of Patent: February 12, 2008Assignee: Silicon Light Machines CorporationInventor: Omar S. Leung
-
Patent number: 7330036Abstract: An engagement probe for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.Type: GrantFiled: July 31, 2003Date of Patent: February 12, 2008Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Malcolm Grief
-
Patent number: 7330025Abstract: A touch-down counter is provided that maintains a count of how many times integrated circuits are placed into contact with a contactor in a test handler. The test handler has a work press that places integrated circuits into contact with pogo pins in the contactor. The pins are subject to wear and should be maintained by periodic cleaning. The touch-down counter has a sensor such as a non-contact Hall effect sensor that is attached to the contactor. A magnet is affixed to the side of the work press. When the work press comes into the vicinity of the sensor, the sensor detects the presence of the magnet and registers a contactor touch-down event. A lifetime count of touch-down events may be displayed on the counter. When a recommended threshold value of touch-down events has been exceeded, a test system operator can remove the contactor from use for cleaning.Type: GrantFiled: November 23, 2005Date of Patent: February 12, 2008Assignee: Altera CorporationInventors: Ronald M. Beach, James Stephen Paine, Joseph W. Foerstel
-
Patent number: 7330024Abstract: A power supply device for supplying source current to an electronic device comprises: a current output unit for outputting output current including at least the source current as a component of the current thereof; a connection resistor which electrically connects the current output unit and the electronic device for supplying the source current to the electronic device; a low-pass filter for allowing the output voltage of the current output unit to pass through; a differential detection unit for detecting the electric potential difference between the output voltage of the low-pass filter and the electric potential at the device-side terminal of the connection resistor; and a parallel load unit which is connected to the output terminal of the current output unit in parallel with the connection resistor, and which has a function of consuming a partial current which is a part of the output current of the current output unit in a case that the electric potential difference detected by the differential detectionType: GrantFiled: November 21, 2005Date of Patent: February 12, 2008Assignee: Advantest CorporationInventor: Yoshihiro Hashimoto
-
Patent number: 7330021Abstract: A substrate table and method for supporting and transferring a substrate are provided. The substrate table includes a segmented stage having an upper surface for supporting a substrate, and an end effector. The end effector includes two or more spaced apart fingers and an upper surface for supporting a substrate. The end effector is at least partially disposed and moveable within the segmented stage such that the fingers of the end effector and the segmented stage interdigitate to occupy the same horizontal plane. The segmented stage is adapted to raise and lower about the end effector.Type: GrantFiled: December 21, 2004Date of Patent: February 12, 2008Assignee: Applied Materials, Inc.Inventors: Shinichi Kurita, Emanuel Beer, Hung T. Nguyen, Benjamin Johnston, Fayez E. Abboud
-
Patent number: 7330044Abstract: A semiconductor testing system including an input; a display; multiple testing units; a memory in which is stored multiple applications that specify the operating procedure of the testing units and multiple categories that are related to the applications; and a controller that has the function of displaying the categories, displaying on the display the applications relating to the categories selected based on the input from the input, and conducting the applications that have been selected by the input from among the displayed applications and controlling the testing units, and the like.Type: GrantFiled: February 2, 2006Date of Patent: February 12, 2008Assignee: Agilent Technologies, Inc.Inventor: Koji Ishizuka
-
Patent number: 7327158Abstract: A method of detecting thin film transistor (TFT) defects in a TFT-liquid crystal display (LCD) panel, includes, in part, applying a stress bias to the TFTs disposed on the panel; and detecting a change in electrical characteristics of the TFTs. The change in the electrical characteristics of the TFTs may be detected using a voltage imaging optical system or an electron beam. The panel temperature may be varied while the bias stress is being applied. The change in the electrical characteristics is optionally detected across an array of the TFTs.Type: GrantFiled: July 31, 2006Date of Patent: February 5, 2008Assignee: Photon Dynamics, Inc.Inventor: Myungchul Jun
-
Patent number: 7327135Abstract: An exemplary testing apparatus (200) for testing electronic device (280) includes a workbench (210), a conveyance board (221) for supporting the electronic device to be tested and a testing device (270). The conveyance board is slidably positioned on the workbench. The testing apparatus further includes an automatic detection device (250), a high voltage connector (241) and an automatic controller (290). The automatic controller receives a signal sent by the automatic detection device and sends an instruction to control the operation of the high voltage connector to connect a plurality of signal channels. The testing apparatus is safe and can reduce the cost.Type: GrantFiled: June 26, 2006Date of Patent: February 5, 2008Assignees: Innocom Technology ( Shenzhen) Co., Ltd., Innolux Display Corp.Inventor: Jun-Hua Yang
-
Patent number: 7327157Abstract: A switch device includes a switch to be tested with a first terminal and a second terminal as well as a control terminal for controlling a resistance between the first terminal and the second terminal. Furthermore, the switch device includes a resistor as well as means for providing a measuring current across the resistor into the first terminal of the switch to be tested, wherein the control terminal and the first terminal of the switch to be tested are coupled in electrically conductive manner. Furthermore, the switch device includes means for sensing a voltage present due to the measuring current between the control terminal and the second terminal of the switch to be tested, wherein the voltage refers to an operability of the switch to be tested. With the switch device, in particular a greater number of potentially occurring errors of the switch to be tested can be detected as opposed to conventional switch devices.Type: GrantFiled: May 4, 2006Date of Patent: February 5, 2008Assignee: Fraunhofer-Gesellschaft zur angewandten Forschung e.V.Inventor: Michael Hackner
-
Patent number: 7327134Abstract: A method to balance transformer flux among a plurality of transformers is disclosed. The plurality of transformers is connected to a plurality of converters, each transformer having an associated converter. The method comprises determining a reference flux value, measuring an actual flux value for each transformer, and developing a plurality of voltage command signals in relation to a plurality of variance values between the reference flux value and each actual flux value. In response to the voltage command signals being received at a modulator in signal communication with the plurality of converters, the method proceeds by generating a plurality of switching signals to reduce each of the variance values by making available the plurality of switching signals to each of the associated plurality of converters.Type: GrantFiled: July 26, 2006Date of Patent: February 5, 2008Assignee: General Electric CompanyInventors: Haiqing Weng, Kunlun Chen, Rajib Datta, Allen Michael Ritter
-
Patent number: 7327153Abstract: An analog BIST (Built-in Self-Test) module for a load board in a test system for testing Integrated Chips (IC) and other devices-under-test (DUTs). Components of the test module perform test setup, transmission of analog test signals to a DUT, capture of analog and digital test data from the DUT, and on-board analysis of the test data using DSPs without sending the test data to a tester. Modules may be add-on boards to load boards an contain one or more processors and multiple components to test DUTs in parallel, significantly decreasing test and analysis times of a test system such as a Very Low Cost Tester (VLCT).Type: GrantFiled: November 2, 2005Date of Patent: February 5, 2008Assignee: Texas Instruments IncorporatedInventor: Chananiel Weinraub
-
Patent number: 7323861Abstract: One embodiment of the invention provides a standardization module for use in standardizing tester channels of a tester unit using a standardization unit for making contact with contact faces which are connected to the tester channels and for standardizing the tester channels. The standardization module has a first surface on which first contact faces are arranged in such a way that contact can be made by a contact making card of the tester unit with the first contact faces in a defined fashion. The standardization module has a second surface on which second contact faces are arranged in such a way that contact can be made with the second contact faces using the standardization unit. Each of the first contact faces is respectively connected to one of the second contact faces.Type: GrantFiled: February 25, 2005Date of Patent: January 29, 2008Assignee: Infineon Technologies AGInventor: Thorsten Bucksch
-
Patent number: 7323890Abstract: A multi-point electrical probe for testing location-specific electrical properties on circuit boards. Four generally parallel, electrically conducting probe arms are produced preferably by wafer-based techniques, although any even number of probe arms between two and 64 may be used. The precision of wafer-based manufacturing techniques permits miniaturization beyond that which is conventionally obtained by assembling discrete components. The probe arms are generally flexible, and may be shaped suitably to accommodate a particular circuit geometry. The probe and/or the sample under test may be precisely located by suitable translation and/or rotation stages, which may optionally be placed under computer control. A suitable wiring diagram is provided, and preferable manufacturing techniques are discussed.Type: GrantFiled: September 30, 2003Date of Patent: January 29, 2008Assignee: Capres APSInventors: Christian Leth Petersen, Francois Grey, Peter Boggild
-
Patent number: 7323893Abstract: A probe device includes a tester; a probe card; a base card holder; an auxiliary card holder for adaptively mounting the probe card to the base card holder; and a conversion ring for allowing the auxiliary card holder to be fitted to the base card holder. In the probe device, the base card holder is configured to accommodate any one of selected different conversion rings and the conversion ring is the one chosen from the different conversion rings according to the probe card.Type: GrantFiled: September 19, 2006Date of Patent: January 29, 2008Assignee: Tokyo Electron LimitedInventor: Masayuki Noguchi
-
Patent number: 7323859Abstract: An auto-measuring universal meter is disclosed. The auto-measuring universal meter includes a main unit having a display and a single button. A pair of test probes is electrically connected to the main unit in a removable manner to detect a first input signal; an inductive clamp is formed on and electrically connected to the main unit for gripping a current-carrying conductor to detect a second input signal indicative of an alternating/direct current flowing through the current-carrying conductor. The main unit is designed so as to take measurement of the input signals in a self-judging mode based on the presence of and/or the differences between the input signals so that the alternating/direct current can also be measured.Type: GrantFiled: July 19, 2006Date of Patent: January 29, 2008Assignee: APPA Technology Corp.Inventors: Win-Throng Chen, Shou-Hua Lin
-
Patent number: 7323862Abstract: A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.Type: GrantFiled: April 25, 2006Date of Patent: January 29, 2008Assignee: Credence Systems CorporationInventors: Romain Desplats, Patricia Le Coupanec, William K. Lo, Philippe Perdu, Steven Kasapi
-
Patent number: 7323891Abstract: A method of and testing jig for sequentially testing front and rear surfaces of a semiconductor chip is shown. The testing jig includes a support package having a first cavity over which the semiconductor chip mounts; an infrared filter affixed relative to the first cavity and attached to a rear surface of the semiconductor chip; and a test substrate having a second cavity exposing the infrared filter and upon which the support package mounts. Front and rear surfaces of the semiconductor chip can be conveniently and sequentially tested. Because the testing jig includes the infrared filter and the heat pad, heat can be easily transmitted to the defective chip.Type: GrantFiled: May 24, 2006Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Jong Kim, Ho-Jeong Choi, Chan-Soon Park