Abstract: Sorting handler for a burn-in tester including two DC testing parts and two unloading buffers on opposite sides of a burn-in board at a working post in a line with a main working line respectively, one pair of a loader part for supplying new devices and an unloader part for receiving tested good devices on each of side parts of a body, so that two insert/remove pickers carry out a work continuously in which two insert/remove pickers move along the main working line in both directions with reference to the burn-in board, to remove the devices from the burn-in board, and insert devices to be tested in the space in turn, thereby improving a test productivity per a unit time period.

Abstract: A method and apparatus is provided for characterizing a contactor for automated semiconductor device testing, the method first comprising placing the contactor on a contactor test board positioned within an automated test apparatus. A first probe of the automated test apparatus is contacted to a conductive layer of the contactor test board, and a second probe is placed on a contactor pin of the contactor, wherein the contactor pin is operable to linearly translate within the contactor. A predetermined pressure is applied to the contactor pin via the second probe, wherein the contactor pin is translated toward the contactor test board. An electrical characteristic of the contactor pin is measured between the first probe and the second probe and compared to a desired electrical characteristic, wherein a condition of the contactor pin is determined, based on the comparison of the measured electrical characteristic and the desired electrical characteristic.

Abstract: A thermal feedback loop controls leakage current during burn-in of a circuit.

Abstract: A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer formed over the buried oxide layer, and a top oxide layer formed over the silicon layer. Adjacent an edge of the top oxide layer, a dual gate oxide is formed. The dual gate oxide allows both specific-on-resistance and breakdown voltage of the device to be optimized.

Abstract: An exemplary hi-pot testing device (2) includes a testing table (20), a transfer table (21) movably supported on the testing table and configured to support a product (200) to be tested, and a hi-pot testing signal generator (27) under the testing table. The transfer table includes a top surface and a bottom surface, a first current input portion (23) at the bottom surface (202), a first power connector (234) embedded at the top surface, and electrically connecting to the first current input portion, and a first signal cable connector (25) arranged on the top surface. The first signal cable connector is grounded and configured to enable the product to be grounded. The hi-pot testing signal generator is configured to electrically connect with and electrically disconnect from the first current input portion of the transfer table.

Abstract: An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

Abstract: The invention relates to a method for determining a characteristic of a semiconductor sample forming a surface. The method comprises the steps: simultaneously illuminating an area on the surface of a semiconductor sample with superimposed exciting light beams with a plurality of wavelengths, modulating the light beam of the different wavelengths with the same frequency, but different phases, selecting a modulation function and its phases in such a way, that the sum of the photon fluxes of all light beams at all times lies within a tolerance range, the tolerance range being considerably smaller than the sum of all photon fluxes, simultaneously phase-dependent measuring of the components of the surface photo voltage caused by the different light beams and determining the characteristic of the semiconductor sample from the relationships between the components and the respective wavelengths. Furthermore a device for carrying out such a method is described.

Abstract: A method for testing a contact region of a semiconductor module having a circuit arrangement is disclosed. In one embodiment, the semiconductor module is heated by an electrical heating current flow and the electrical and/or thermal quality of a plurality of contacts provided in the contact region is determined in the process from a temperature-dependent measurement quantity. The heating current flow is formed by a plurality of heating current pulses. The application of the heating current pulses leads to different phases of the measurement quantity. The different phases are assigned to the different contacts and evaluated correspondingly for determining the electrical and/or thermal quality of the contacts.

Abstract: A circuit configuration providing a diagnostic signal for a power switching device which switches a load has a test circuit, a filter device, a validation device, and a coding device. The test circuit tests the power switching device and generates error symptoms for characterizing error types of different priorities. The filter device, depending on an activation signal activating the power switching device, provides a validity signal for the generated error symptoms. The validity signal specifies the validity of the corresponding error symptom in each case. The validation device validates a generated error symptom depending on the associated validity signal in each case and validates the validated activation signal and from this generates a group of is states and the associated complementary states. The coding device codes the states and complementary states depending on the priorities of the error types assigned to the states and complementary states.

Abstract: Device characterization performed with a test system including a fixture and multiple frequency dependent test boards. In one embodiment, testing is performed with multiple sets of input and output test boards wherein each set is frequency dependent at different frequencies. In some examples, the test board includes an impedance transformer that is a quarter wave length of the fundamental frequency (f0) of a frequency of which the board is dependent. In some examples, S-parameters and load pull measurements are obtained for the device under test with the test boards at different frequencies.

Abstract: Systems and methods for monitoring power in a conductor. A flex circuit may include multiple layers including a voltage sensing layer, a coil layer, and a ground layer. The coil layer includes traces that form a coil structure around a conductor when the flex circuit is wrapped around the conductor. The coil layer generates a voltage that may be integrated to determine a current in the conductor. When the flex circuit is wrapped around the conductor, the voltage sensing layer is closest to the conductor. The voltage sensing layer forms a capacitor with the conductor. Using an adjustable capacitive voltage divider, the voltage of the conductor may be determined from a voltage signal received from the voltage sensing layer.

Abstract: A test apparatus for testing electronic devices, comprising a control section for generating control signals based on a test program set in advance to test the electronic devices, a plurality of test modules for generating test signals to be supplied to the electronic devices on the basis of the control signals, a device interface having connectors, provided in correspondence to the plurality of test modules, for supplying the test signals generated by corresponding test modules to predetermined pins of the electronic devices, wherein a test module for generating source power to be supplied to the electronic device outputs the source power only when it is connected with a connector set in advance among the plurality of connectors and does not output source power when it is not connected with the connector set in advance.

Abstract: An electronic residential electricity meter includes a base assembly having a main body with a current transformer mounted thereto. A first conductor is mounted through a window of the current transformer. The current transformer being operable in the presence of a direct current. The meter also includes an electronic module that has only one printed circuit board and a microcomputer for executing meter data operations. The current transformer and the first conductor are in electrical communication with the electronic module.

Abstract: A semi-conductor component test process, and a system for testing semi-conductor components, with which several different semi-conductor-component tests can be conducted in succession. A computer installation, in particular a test apparatus is provided, with which test result data obtained from a first test is evaluated, and which causes a further test provided after the first test), to be performed in an amended fashion, or to be dispensed with, depending on the test result data obtained from the first test.

Abstract: An apparatus for mitigating condensation formation on a device interface board during low-temperature semiconductor device testing includes a nozzle. The nozzle includes an input orifice for receiving gas from a gas source and at least one output orifice for discharging gas from the nozzle against a surface of the device interface board. The area of the at least one output orifice is substantially greater than the area of input orifice.

Abstract: A performance board for allowing a device under test and a testing apparatus to be electrically coupled with each other, includes a base substrate on which the device under test is mounted, a first adaptor part provided with a plurality of coaxial connectors for allowing a plurality of coaxial cables electrically coupled to a plurality of first pins of the device under test respectively and the testing apparatus to be electrically coupled with each other and a second adaptor part provided with a plurality of via holes for allowing a plurality of wirings electrically coupled to a plurality of second pins of the device under test respectively and the testing apparatus to be electrically coupled with each other.

Abstract: An inspection method including measuring a height of a load cell of a load detecting mechanism using a laser length measuring mechanism, obtaining a first rise amount of the load detecting mechanism from a measuring position of the load detecting mechanism up to a contact starting position, measuring a height of an electrode of a wafer using the laser length measuring mechanism, and obtaining a second rise amount of a main chuck up to the contact starting point of the electrode with the probe based on a difference between a measuring height of the electrode of the wafer and the measuring height of the load detecting mechanism.

Abstract: An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.

Abstract: A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections is provided. The method may include providing a device socket for connecting the set of top-side connections and the set of bottom-side connections to a tester. The method may further include providing a device hood for connecting the set of top-side connections to a respective first end of each of a plurality of interconnects in the device hood, wherein a second end of each of the plurality of interconnects in the device hood connects the set of top-side connections to the device socket. The method may further include testing the semiconductor structure using the tester. The semiconductor structure may include at least one integrated circuit to be tested.

Abstract: A connection apparatus includes a switch; a control signal connector that transmits a switching signal, sent from a controller, to the switching means; a first plurality of connectors that are connected to the switch and that are to be connected to a plurality of measurement connectors included in first measuring apparatus for measuring a first electrical characteristic of the device under test; and a second plurality of connectors that are connected to the switch and that are to be connected to a plurality of measurement connectors included in second measuring apparatus for measuring a second electrical characteristic of the device under test. In accordance with the switching signal sent from the controller via the control-signal connector, the switch performs switching so that either the first plurality of connectors or the second plurality of connectors are electrically connected to the device under test.