Abstract: A wide bandwidth attenuator input circuit for a measurement probe has a Z0 attenuator circuit coupled in series with a compensated RC attenuator circuit. The series attenuator elements of the Z0 and the compensated RC attenuator circuits are coupled via a controlled impedance transmission line to the shunt attenuator elements of the Z0 and the compensated RC attenuator circuits. The shunt element of the Z0 attenuator element terminates the transmission line in its characteristic impedance. The junction of the series and shunt attenuator elements are coupled to the input of a buffer amplifier. At low and intermediate frequencies, the compensated RC attenuator circuit attenuates an input signal while at high frequencies, the compensated RC attenuator circuit acts as a short and the Z0 attenuator circuits attenuates the input signal.

Abstract: A method of detecting defects in a patterned substrate includes positioning a charged-particle-beam optical column relative to a patterned substrate, the charged-particle-beam optical column having a field of view (FOV) with a substantially uniform resolution over the FOV; operating the charged-particle-beam optical column to acquire images of a region of the patterned substrate lying within the FOV by scanning the charged-particle beam over the patterned substrate; and comparing the acquired images to a reference to identify defects in the patterned substrate.

Abstract: A probe used for a high electric current. The prove comprises an outer pipe having a cylindrical configuration which is opened at upper and lower ends thereof; a plunger installed in an upper part of the outer pipe to be elastically extended out of and retracted into the outer pipe, and brought into contact with a contact terminal of a test object; a contact member installed in a lower part of the outer pipe and electrically connected with a contact terminal of a circuit board; and a plurality of contact wires installed at a region where the plunger and the contact member are engaged with each other, to electrically connect the plunger to the contact member, and each having one end which is bent outward.

Abstract: A test tray for a handler for testing semiconductor devices is disclosed which is capable of reducing the costs and time taken for replacement of carrier modules, and achieving an enhancement in workability.

Abstract: A method and apparatus for maximizing the usage of a testhead of an in-circuit tester is presented. A testhead execution supervisor interfaces between a testhead controller and a graphical user interface used to enter manual tests. The testhead execution supervisor adds tests to be submitted to the testhead to one or more queues according to a priority scheme. Tests may be submitted to the testhead execution supervisor both as manual tests entered via the graphical user interface and as automatically generated tests generated by an automatic debug module. The automatic debug module may automatically generate tests for execution by the testhead that are executed when the testhead is idle, for example when no higher priority manual tests are scheduled.

Abstract: A system on chip (SOC), comprises an external interface that receives test configuration data, transmits test result data, and that transmits and receives application data. A plurality of SOC components, each including an integrated system test (IST) module, wherein at least one of the SOC components includes a controller that communicates with the external interface. At least one of the plurality of SOC components communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing the plurality of SOC components.

Abstract: A central test facility transmits wirelessly test data to a local test facility, which tests electronic devices using the test data. The local test facility transmits wirelessly response data generated by the electronic devices back to the central test facility, which analyzes the response data to determine which electronic devices passed the testing. The central test facility may provide the results of the testing to other entities, such as a design facility where the electronic devices were designed or a manufacturing facility where the electronic devices where manufactured. The central test facility may accept requests for test resources from any of a number of local test facilities, schedule test times corresponding to each test request, and at a scheduled test time, wirelessly transmits test data to a corresponding local test facility.

Abstract: A method for use with automatic test equipment (ATE) having sites, each which accommodates a device under test (DUT), includes defining an object for use with the plural sites, where the object is to contain data associated with at least some of the plural sites, and where the object determines which sites are active. The method also includes using the object during testing of DUTs by the ATE.

Abstract: A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.

Abstract: A probe assembly suitable for making test measurements using test signals having high currents. The disclosed probe assembly provides for a test signal exhibiting relatively low inductance when compared to existing probe assemblies by preferably reducing the electrical path distance between the test instrumentation and the electrical device being tested.

Abstract: A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.

Abstract: A hard disk drive system includes an external interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. The hard disk drive system includes a system on chip (SOC) that includes a controller and a read/write channel that communicates with the controller and that includes an integrated system test (IST) module that communicates with the external interface. A memory module communicates with the SOC and includes memory and an IST module. The hard disk drive system includes a spindle/voice coil motor driver module that includes an IST module. At least one of the IST modules is a master IST module that receives the test configuration data and that configures the IST modules for testing at least one of the controller, the read/write channel, and the memory module.

Abstract: A probe station for probing a test device has a chuck element for supporting the test device. An electrically conductive outer shield enclosure at least partially encloses such chuck element to provide EMI shielding therefor. An electrically conductive inner shield enclosure is interposed between and insulated from the outer shield enclosure and the chuck element, and at least partially encloses the chuck element.

Abstract: A current sensor includes a first magnetic core that surrounds a portion of a conductor as a current path and has gaps therein, each of which is defined by adjacent ends spaced from each other by a first distance, a magnetic sensing element placed in at least one of the gaps, and a second magnetic core placed near the surrounded portion of the conductor to divide the conductor into channels. The second magnetic core is spaced from the first magnetic core by a second distance smaller than the first distance. Therefore, a magnetic resistance of the second magnetic core is smaller than that of the first magnetic core in a magnetic circuit formed by the first and second magnetic cores. As a result, a disturbance magnetic field mainly passes through the second magnetic core.

Abstract: An assembly including a processor socket having a cut region. The assemble further including a probe board having a repeater positioned in alignment with the cut region. The repeater is to receive at least a first signal. The repeater is to tap the first signal. The tapped first signal is to be transmitted to a first device. The repeater is also to reinject the first signal, and the reinjected first signal to be transmitted to a processor.

Abstract: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.

Abstract: The present invention provides a magnetic sensing device capable of stably sensing a signal magnetic field with high sensitivity by suppressing occurrence of a hysteresis to reduce 1/f noise. A magnetic sensing device has a stacked body including a pinned layer having a magnetization direction pinned to a predetermined direction (Y direction), a free layer having a magnetization direction which changes according to an external magnetic field and, when the external magnetic field is zero, becomes parallel to the magnetization direction of the pinned layer, and an intermediate layer sandwiched between the pinned layer and the free layer. Consequently, as compared with the case where the pinned layer and the free layer have magnetization directions which are orthogonal to each other when the external magnetic field is zero, variations in the spin directions of magnetic domains in the free layer can be reduced.

Abstract: An electro-optical device includes a first substrate that holds an electro-optical material, a first IC that is mounted on the first substrate and that has a plurality of first terminals, a plurality of second terminals formed on the first substrate to be connected to the first terminals, respectively, a plurality of wiring lines formed on the first substrate, first substrate crack diagnostic terminal pairs that are included in the plurality of the first terminals and that are used for diagnosing whether a crack occurs in the first substrate, second substrate crack diagnostic terminal pairs that are included in the plurality of second terminals and that are connected to the first substrate crack diagnostic terminal pairs, respectively, a substrate crack diagnostic conductive pattern that connects the second substrate crack diagnostic terminal pairs and that extends around an outer periphery of the first substrate, a substrate crack diagnostic unit provided in the first IC to diagnose whether the first substra

Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.