Patents Examined by Hoa B. Trinh
  • Interconnect structure and method of forming same
    Patent number: 10157866
    Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Tapeless leadframe package with underside resin and solder contact
    Patent number: 10147673
    Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 4, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Substrate and package structure
    Patent number: 10141281
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Method of forming surface protrusions on an article and the article with the protrusions attached
    Patent number: 10132836
    Abstract: A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.
    Type: Grant
    Filed: May 9, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John Knickerbocker, Yang Liu, Maurice Mason, Lubomyr T. Romankiw
  • Wafer bonding process and structure
    Patent number: 10128209
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Lan-Lin Chao, Cheng-Tai Hsiao, Xin-Hua Huang, Hsun-Chung Kuang
  • Semiconductor package and fabrication method thereof
    Patent number: 10128212
    Abstract: A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die and the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Resin composite, semiconductor device, and method of manufacturing the semiconductor device
    Patent number: 10106683
    Abstract: A resin composite includes a maleimide resin powder and a resin having a glass transition point that is lower that the glass transition point of the maleimide resin. The resin having a glass transition point that is lower than that of the maleimide resin may be an epoxy resin. Then, the resin composite may be cured at the curing temperature of the epoxy resin. The maleimide resin powder is mixed in an amount ranging from 50 weight % to 80 weight % with respect to the epoxy resin.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 23, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuko Nakamata, Yuji Ichimura
  • Side view light emitting diode package
    Patent number: 10096756
    Abstract: A side view LED package for a backlight unit includes a package body having a cavity with an inclined inner sidewall, first and second lead frames arranged in the package body, the cavity of the package body exposing a portion of at least one of the first and second lead frames placed in a bottom of the cavity to outside, a light emitting diode chip mounted on the bottom of the cavity to be electrically connected to the first and second lead frames, and a transparent encapsulant arranged in the cavity surrounding the light emitting diode chip. The cavity has a depth larger than a mounting height of the light emitting diode chip and not exceeding six times of the mounting height. The height of the sidewall is shortened to improve beam angle characteristics of emission light, increase light quantity, and prevent a molding defect of the sidewall.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Wook Kim, Yoon Suk Han, Young Jae Song, Byung Man Kim, Jae Ky Roh, Seong Jae Hong
  • Integrated system and method for source/drain engineering
    Patent number: 10090147
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 2, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Chun Yan, Xinyu Bao, Melitta Manyin Hon, Hua Chung, Schubert S. Chu
  • Semiconductor package and method for forming the same
    Patent number: 10068822
    Abstract: A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region; subsequently, disposing at least one die structure onto the active region of the substrate respectively; and then injecting a molding compound flowed into the gap region, to mold the flow hindering supporter and the die structure with the molding compound.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Method and processing apparatus for performing pre-treatment to form copper wiring in recess formed in substrate
    Patent number: 10068798
    Abstract: There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a surface of the substrate that defines the recess, and forming a seed layer on the barrier layer. The method further includes at least one of etching the barrier layer and etching the seed layer. In the at least one of etching the barrier layer and etching the seed layer, the substrate is inclined with respect to an irradiation direction of ions while rotating the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 4, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroyuki Toshima, Tatsuo Hatano, Shinji Furukawa, Naoki Watanabe, Naoyuki Suzuki
  • Semiconductor device
    Patent number: 10068861
    Abstract: Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 4, 2018
    Assignee: ChipMOS Technologies Inc.
    Inventor: Kun-Shu Chuang
  • Electronic device
    Patent number: 10049999
    Abstract: A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one Through Silicon Via (TSV), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at least one TSV. The at least one active chip may be a memory chip and a non-memory chip in a vertically stacked (3D) configuration, connected through an electrical path that includes the TSV of the dummy chip. Embodiments may include multiple memory chips and dummy chips.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seijin Kim
  • Electronic module comprising fluid cooling channel and method of manufacturing the same
    Patent number: 10037972
    Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Martin Gruber, Wolfram Hable
  • Light-emitting element
    Patent number: 10002991
    Abstract: A light-emitting element, comprises a light-emitting stack comprising an active layer; a window layer on the light-emitting stack, wherein the window layer has a surface opposite to the light-emitting stack; and an insulative layer on the surface, wherein the surface comprises a cavity and the insulative layer substantially conformally covering the cavity, and wherein the insulative layer has a first refractive index equal to or smaller than 1.4.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 19, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Wen-Luh Liao, Chun-Yu Lin, Kun-De Lin
  • Vertical multi-batch magnetic annealing systems for reduced footprint manufacturing environments
    Patent number: 10003018
    Abstract: Embodiments are described for annealing systems and related methods to process microelectronic workpieces using vertical multi-batch perpendicular magnetic annealing systems that allow for a side-by-side configuration of multiple annealing systems to satisfy reduced footprint requirements.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 19, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Saito Makoto, Noel O'Shaughnessy, Toru Ishii, David Hurley
  • Packages with stacked dies and methods of forming the same
    Patent number: 9984999
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Dean Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Interconnect structures and methods of formation
    Patent number: 9984976
    Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: May 29, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yana Cheng, Yong Cao, Srinivas Guggilla, Sree Rangasai Kesapragada, Xianmin Tang, Deenesh Padhi
  • Manufacturing method of a flip-chip light emitting diode package module
    Patent number: 9978915
    Abstract: The instant disclosure relates to a flip-chip LED package module and a method of manufacturing thereof. The method of manufacturing flip-chip LED package module comprises the following steps. A plurality of LEDs is disposed on a carrier. A packaging process is forming a plurality of transparent lens corresponding to LEDs and binding each other by a wing portion. A separating process is proceeding to form a plurality of flip-chip LED structures without the carrier. A bonding process is proceeding to attach at least one flip-chip LED structure on the circuit board.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 22, 2018
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Ming-Kun Weng, Meng-Sung Chou
  • Display driver integrated circuit and method of manufacturing the same
    Patent number: 9960193
    Abstract: A display driver integrated circuit and a method of manufacturing the same are provided. The method of manufacturing a display driver integrated circuit (DDI) including a first area, a second area, and an overlapping area in which the first area and the second area overlap each other includes forming a first pattern in the first area using a first reticle; and forming a second pattern in the second area using a second reticle, and ends of the first pattern and the second pattern are connected within the overlapping area and the first area and the second area are asymmetrically set based on the overlapping area such that the overlapping area includes only a metal line.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Park, Siwoo Kim