Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.

Abstract: A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Abstract: The present disclosure relates to a chip package and a method for forming the same. The chip package comprises a carrier pad, a chip, and a plurality of second conductive bumps, and a molding compound. The carrier pad has a first surface with a plurality of first conductive bumps formed thereon. The chip has an active surface. One end of each of the plurality of second conductive bumps is electrically coupled to the active surface, and the other end of each of the plurality of second conductive bumps is electrically coupled to the first conductive bumps. The molding compound encapsulates the chip and completely fills space between the carrier pad and the chip.

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: According to one embodiment, a first frame includes a first thin plate section and a first thick plate section. A second frame includes a second thin plate section and a second thick plate section. A semiconductor chip includes a first electrode bonded to a first inner surface of the first thin plate section of the first frame, and a second electrode bonded to a second inner surface of the second thick plate section of the second frame. A resin layer seals the semiconductor chip, but leaves exposed the first outer surface of the first frame and the second outer surface of the second frame.

Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

Abstract: A method for making a leadframe includes removing a group of parallel, strip-shaped electrical conductors from a metal sheet, embedding end portions of the conductors in molding compound defining a leadframe body, and separating the conductors from each other, such that portions of the conductors remain encapsulated in the molding compound while other portions remain exterior to the molding compound and define leads of the resulting leadframe.

Abstract: A semiconductor device includes: a package including a base plate and a side wall located on a perimeter of the base plate; a semiconductor element on the base plate; and a lid joined to a top of the side wall and covering the semiconductor element, wherein a first curved surface is located inside the package at the top of the side wall, a second curved surface is located on a perimeter of an undersurface of the lid, and the first curved surface of the side wall contacts the second curved surface of the lid.

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract: Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.

Abstract: Provided are a semiconductor die and a semiconductor package. The semiconductor package includes: a monolithic die; a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and an upper electrode and a lower electrode disposed above and below the monolithic die.

Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.

Abstract: A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.

Abstract: A method of forming an assembly of a substrate and a flip-chip having solder balls thereon, the method having steps of: placing the flip chip with the solder balls in contact with the substrate to form a first interim assembly at a first predetermined temperature; providing an encapsulant to the first interim assembly to form a second interim assembly at a second predetermined temperature that is lower than a melting temperature of the solder balls and higher than the first predetermined temperature; and subjecting the second interim assembly to an environment of a third predetermined temperature that is sufficient to melt the solder balls. An encapsulant for use in forming an assembly of a substrate and a flip-chip having solder balls thereon, the encapsulant consisting essentially of: an epoxy resin; an anhydride curing agent; a fluxing agent having a hydroxyl (—OH) group; and an inorganic filler.

Abstract: To improve light extraction efficiency. A semiconductor light-emitting device wherein each layer is formed of a Group III nitride-based compound semiconductor. The light-emitting device comprises a sapphire substrate having a plurality of stripe-patterned grooves 11 arranged in parallel to a first direction (x axis) on a surface of the substrate 10, a dielectric 15 discontinuously formed at least in the first direction on the surface 10a of the sapphire substrate and in the grooves 11, a base layer being grown on side surfaces of the grooves and made of a Group III nitride-based compound semiconductor covering the surface 10a of the sapphire substrate and the top surfaces 15a of the dielectrics 15, and a device layer constituting a light-emitting device formed on the base layer.

Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Abstract: A semiconductor device includes a metal substrate, semiconductor elements, wires, a control terminal, a main electrode terminal, a control substrate, a cover, a sealing resin, a case, and an insulator. The metal substrate includes a metal plate, an insulating layer formed on the top surface of the metal plate, and electrode patterns provided on the insulating layer. The semiconductor elements are secured to different ones of the electrode patterns by solder. The sealing resin seals the components within the case, such as the semiconductor elements. The insulator covers a portion of the surface of the insulating layer and at least a portion of the edge of each electrode pattern.