Abstract: The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.

Abstract: A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area.

Abstract: A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion.

Abstract: A semiconductor manufacturing method includes attaching a first die to a substrate panel. The method also includes applying a mold compound after attaching the first die to the substrate panel to the first die and the substrate panel. The method further includes thinning the first die and the mold compound after applying the mold compound. Attaching the die to the substrate panel before thinning eliminates usage of a carrier wafer when processing thin semiconductors.

Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer, wherein the first metal line is embedded in the passivation layer.

Abstract: An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels.

Abstract: A fiber-containing resin substrate for collectively sealing a semiconductor devices mounting surface of a substrate having the semiconductor devices mounted thereon or a semiconductor devices forming surface of a wafer having semiconductor devices formed thereon, includes: a resin-impregnated fiber base material obtained by impregnating a fiber base material with a thermosetting resin and semi-curing or curing the thermosetting resin; and an uncured resin layer containing an uncured thermosetting resin and formed on one side of the resin-impregnated fiber base material.

Abstract: An electronic apparatus includes a packaging enclosure, first and second die pads disposed within the packaging enclosure, first and second semiconductor die disposed on the first and second die pads, respectively, a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure, a plurality of packaging posts disposed within the packaging enclosure and extending inward from opposite sides of the packaging enclosure between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads, and a plurality of wire bonds disposed within the packaging enclosure. Each packaging post of the plurality of packaging posts is connected via a first wire bond of the plurality of wire bonds to the first semiconductor die and via a second wire bond of the plurality of wire bonds to the second semiconductor die.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: An integrated circuit includes an interposer die having a surface, a first die mechanically and electrically attached to the surface of the interposer die, and a second die only mechanically attached to the surface of the interposer die using a die attach adhesive.

Abstract: Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. The first insulation layer has a trench disposed in a portion of the first insulation layer to expose the plurality of bumps.

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract: A lighting apparatus includes a substrate, a plurality of light-emitting dies, a continuous encapsulation structure, and a gel. The plurality of light-emitting dies are disposed on the substrate and spaced apart from one another. The light-emitting dies each are covered with a respective individual phosphor coating conformally. The continuous encapsulation structure has a curved surface disposed over the substrate and encapsulates the light-emitting dies within. The gel is disposed between the encapsulation structure and the phosphor coating for each of the light-emitting dies. The gel contains diffuser particles. The lighting apparatus has a substantially white appearance in an off state when the plurality of light-emitting dies is turned off.

Abstract: A method for applying a pressure-sensitive gel material during assembly of an array of pre-singulated packaged semiconductor devices. In the method, pressure-sensitive gel material is dispensed onto a first semiconductor device of the array, where the first semiconductor device is disposed within a first cavity. A first curing process is performed to partially cure the pressure-sensitive gel material in the first cavity. Pressure-sensitive gel material is then dispensed onto another semiconductor device of the array, where the other semiconductor device is disposed within another cavity. The first curing process is initiated before the dispensing of the pressure-sensitive gel material inside of the other cavity is completed and initially cures pressure-sensitive gel material for fewer than all of the pre-singulated packaged semiconductor devices of the array.

Abstract: A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.

Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Abstract: A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.

Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.