Patents Examined by Hoa B. Trinh
  • Method for manufacturing semiconductor apparatus
    Patent number: 9177938
    Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 3, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Motoaki Tani, Keishiro Okamoto
  • Power semiconductor module and method of manufacturing the same
    Patent number: 9171774
    Abstract: A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 27, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masataka Shiramizu, Ming Shang
  • Semiconductor light emitting device with thick metal layers
    Patent number: 9172001
    Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A portion of a sidewall the device adjacent to one of the first and second metal layers is reflective.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 27, 2015
    Assignee: Koninklijke Philips N.V.
    Inventor: Marc Andre Desamber
  • Induction-coupled clock distribution for an integrated circuit
    Patent number: 9172383
    Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 27, 2015
    Assignee: Broadcom Corporation
    Inventors: David Chang, Ajat Hukkoo
  • Semiconductor device and method of manufacturing same
    Patent number: 9165987
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: October 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • Light-emitting element
    Patent number: 9153747
    Abstract: A light-emitting element includes a light-emitting stack which has an active layer, and a non-oxide insulative layer below the light-emitting stack, wherein a refractive index of the non-oxide insulative layer is less than 1.4.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 6, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Wen-Luh Liao, Chien-Chung Hsu, Yao-Ru Chang, Shih-I Chen, Chia-Liang Hsu
  • Semiconductor device and method of manufacturing the same
    Patent number: 9153510
    Abstract: A semiconductor device includes a semiconductor substrate provided with a predetermined element and having wirings formed on its main surface connected to back wirings by a plurality of through silicon vias (TSVs), and a conductive cover which covers the main surface of the semiconductor substrate. The semiconductor substrate and the conductive cover are bonded to each other with a conductive bonding member. The TSV bonded to the conductive cover with the conductive bonding member is connected to an external electrode pad to which a ground potential is supplied.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masafumi Sugimoto, Eiichi Hosomi, Atsushi Murakawa, Kazumi Takahashi, Kazuhito Higuchi, Susumu Obata
  • Rotating curing
    Patent number: 9147584
    Abstract: A system for and a method of curing a material is provided. A material, such as an underfill material, is rotated during a curing process. The curing system may include a chamber, a holder to support one or more workpieces, and a rotating mechanism. The rotating mechanism rotates the workpieces during the curing process. The chamber may include one or more heat sources and fans, and may further include a controller. The curing process may include varying the rotation speed, continuously rotating, periodically rotating, or the like.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing Ruei Lu, Yu-Chih Liu, Ming-Chung Sung, Wei-Ting Lin, Chien-Kuo Chang
  • Method for forming separate narrow lines, method for fabricating memory structure, and product thereof
    Patent number: 9147692
    Abstract: A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: September 29, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Integrated circuit system employing alternating conductive layers
    Patent number: 9147654
    Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn
  • Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer
    Patent number: 9142532
    Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: September 22, 2015
    Assignee: BONDTECH CO., LTD.
    Inventors: Tadatomo Suga, Akira Yamauchi
  • Junction and electrical connection
    Patent number: 9142518
    Abstract: A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 22, 2015
    Assignee: NAPRA CO., LTD.
    Inventor: Shigenobu Sekine
  • Localized high density substrate routing
    Patent number: 9136236
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 15, 2015
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Semiconductor device and method of manufacturing the same
    Patent number: 9123709
    Abstract: According to one embodiment, a first frame includes a first thin plate section and a first thick plate section. A second frame includes a second thin plate section and a second thick plate section. A semiconductor chip includes a first electrode bonded to a first inner surface of the first thin plate section of the first frame, and a second electrode bonded to a second inner surface of the second thick plate section of the second frame. A resin layer seals the semiconductor chip, but leaves exposed the first outer surface of the first frame and the second outer surface of the second frame.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: September 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koji Tamura
  • Semiconductor device
    Patent number: 9123731
    Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: September 1, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Masaaki Ishida
  • Chip package and method for forming the same
    Patent number: 9123629
    Abstract: The present disclosure relates to a chip package and a method for forming the same. The chip package comprises a carrier pad, a chip, and a plurality of second conductive bumps, and a molding compound. The carrier pad has a first surface with a plurality of first conductive bumps formed thereon. The chip has an active surface. One end of each of the plurality of second conductive bumps is electrically coupled to the active surface, and the other end of each of the plurality of second conductive bumps is electrically coupled to the first conductive bumps. The molding compound encapsulates the chip and completely fills space between the carrier pad and the chip.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: September 1, 2015
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Xiaochun Tan
  • Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HCI solution
    Patent number: 9123785
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 1, 2015
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, INC.
    Inventors: Anh Duong, Errol Todd Ryan
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 9111819
    Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: August 18, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Molded leadframe for PCB-to-PCB connection
    Patent number: 9107333
    Abstract: A method for making a leadframe includes removing a group of parallel, strip-shaped electrical conductors from a metal sheet, embedding end portions of the conductors in molding compound defining a leadframe body, and separating the conductors from each other, such that portions of the conductors remain encapsulated in the molding compound while other portions remain exterior to the molding compound and define leads of the resulting leadframe.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 11, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Nikolaus W. Schunk
  • Copper bump structures having sidewall protection layers
    Patent number: 9093314
    Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ya-Hsi Hwung, Hsin-Yu Chen, Po-Hao Tsai, Yan-Fu Lin, Cheng-Lin Huang, Fang Wen Tsai, Wen-Chih Chiou